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Series Editor Anantha P. Chandrakasan Massachusetts Institute of Technology Cambridge, Massachusetts

For further volumes: http://www.springer.com/series/7236

Yu Cao

Predictive Technology Model for Robust Nanoelectronic Design Foreword by Chenming Calvin Hu

Yu Cao School of ECEE Arizona State University Tempe, AZ, USA [email protected]

ISSN 1558-9412 ISBN 978-1-4614-0444-6 e-ISBN 978-1-4614-0445-3 DOI 10.1007/978-1-4614-0445-3 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2011931530 # Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)

To Xuejue, your dance of the water sings the pebbles of my life

Foreword

The minimum feature size of CMOS technology will approach 10 nm in 10 years. Such aggressive scaling will lead to wonderful benefits to consumers, businesses and the global society. Unfortunately, it will also lead to increased power dissipation, process variations and device drift, posing tremendous new challenges to designing robust circuits. Already, the design complexity and time are increasing at accelerating rates. The lure of early market entry pushes advanced design research to begin much earlier than the completion of device technology development. The need is even clearer where new devices, e.g. FinFET and post-silicon devices are involved. The concept of technology/circuit co-development is no longer just a good idea, it is a necessity. This new paradigm requires predictive SPICE transistor models for future technology generations, including both nanoscale CMOS and post-silicon devices. SPICE models used in circuit design are traditionally extracted from measurements taken on working transistors generated by the technology development process. In stark contrast, predictive SPICE model is created before the physical transistor has been fabricated, thus allowing design research to get an important early start. A predictive model is critical to identifying emergent problems and enable early search for solutions. While integrated semiconductor companies already make significant efforts to generate predictive models, fabless companies and university researchers usually do not have access to them. PTM, a canonical Predictive Technology Model of both transistors and