Prevention of Corner Voiding in Selective CVD Deposition of Titanium Silicide on SOI Device
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Si lines in parallel with linewidth of IBm. The linewidth of oxide cross bars is also I gm. There are a total of 10 cross bars across the silicon lines. SOI wafers with 2200A Si film and about 2000A buried oxide layers were obtained from IBIS Technology Corp. The Si film was thinned down to a final thickness of 200A to 500A through several sequences of thermal oxidation and HF etch steps. The test structure was formed using plasma etching, ion implantation, activation anneal, oxide deposition and oxide etch steps. The wafers were cleaned in SC-1 and SC-2 solutions, and dipped in dilute HF solutions before loading into the load-lock chamber of the CVD system. Figure 1 Test structure with double Si lines formed from patterning the Si on SOI wafer or etching a PECVD Si film on oxidized bulk Si wafer. The Si lines were doped by BF 2 implantation. Ten oxide cross-bars were formed on top of the Si lines. Voiding was expected to occur in the Si lines under the edge of the oxide cross-bars.
Due to the high cost of SOI wafers, test structures were also formed on less expensive bulk Si wafers. Si films were deposited by LPCVD on oxidized Si wafers with 280A, 400A, or 900A of Si thickness. Wafers were then implanted with BF 2 or As at 40-50keV to 3E15. After implantation, the wafers were covered with oxide and annealed at 850'C. Resist patterns and oxide etching were used to define oxide crossbars. After resist stripping and wafer cleaning, the wafers were ready for CVD silicide deposition.
CVD TiSi 2 deposition was carried out in an AG IntegralOne rapid thermal chemical vapor deposition (RTCVD) system. The details of this system were described in a previous paper [121. The deposition temperature was maintained around 780'C. Processing gases were introduced from the upper part of the chamber and distributed to the wafer surface through a perforated quartz plate, which acted as a showerhead. Process gases consisted of TiCI4, SiI 4 , SiH 2Cl2 , and H2. The flow rate of SiH4, SiH 2Cl 2 and H2 were maintained at 61 sccm, 5 sccm, and 1500 sccm, respectively. The TiCh flow was controlled by a UNIT mass flow controller to a range of 0.2ccm - 2 sccm. Pressure was around 300 mTorr. Typical deposition time was 10 sec to 60 sec. Results and Discussion Void formation was difficult to detect by scanning electron microscopy, probably due to the fact that it is difficult to cleave through small isolated voids. Void formation was detected on the cross-sectional samples by transmission electron microscopy. Voids were found to occur near the bottom comer of the sidewall spacer. When voids occurred, the drain current of SOI MOS transistor was found to decrease drastically. Bulk Si wafers with void test structures were evaluated to determine their sensitivity. After 40 sec silicide deposition, wafers with 1000A Si film showed no increase of line resistance. Wafers with 280A Si and 400A Si showed an open circuit after the same deposition. This
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indicated void formation was dependent on Si thickness. Experiments were repeated with a deposit
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