Process-Induced Deformations and Stacking Faults in 4H-SiC
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0911-B07-02
Process-Induced Deformations and Stacking Faults in 4H-SiC Robert S Okojie1, Xianrong Huang2, Michael Dudley2, Ming Zhang3, and Pirouz Pirouz3 1 Sensors and Electronics Branch, NASA, 21000 Brookpark Road, M/S 77-1, Cleveland, OH, 44136 2 Dept. Materials Science and Engineering, State University of New York, Stony Brook, NY, 11794-2275 3 Dept. Materials Science and Engineering, Case Western Reserve University, Cleveland, OH, 44106 ABSTRACT We used Film Stress Measurement (FSM), Transmission Electron Microscopy (TEM), and High-Resolution X-ray Diffraction (HRXRD) techniques to obtain further knowledge with respect to the deformation, warpage, and stacking faults (SF’s) that are induced in n-type 4H-SiC wafers and epilayers when subjected to mechanical polishing and high temperature (1150 oC) processing. INTRODUCTION Silicon carbide semiconductor has been attracting growing attention over the past three decades, particularly due to its potential applications in high power and high temperature electronics and sensors. This is as a result of its superior electrical and high temperature properties over conventional semiconductor materials. A variety of electronic and sensing devices fabricated in single crystal SiC, particularly in the hexagonal 4H- and 6H- polytypes, have been demonstrated and a few are commercially available and deployed in the field. One of the major benefits of SiC electronics is its potential application as a high voltage PiN rectifier diode, which has been demonstrated to block voltage as high as 10 kV [1]. However, the presence of several kinds of structural defects in the crystal has, in general, been largely responsible for the performance of these devices at below theoretical levels. The presence of Stacking Faults (SFs), in particular, is recognized to be the primary defect that degrades the electrical performance of PiN diodes over time [2]. Their deleterious effects are more severe given that they exist (or are generated) in the active region of the device. Two well-established conditions under which these SFs form are during high temperature processing of n-type 4H-SiC and during the forward bias operation of 4H-SiC-based PiN diodes. Under the former condition, SFs that lead to the formation of 3C-like bands in n-type 4H-SiC epilayer doped 1.7 x 1019 cm-3 were discovered after routine thermal oxidation or argon annealing at 1150°C [3]. In the latter case, the SFs were observed to form and enlarge driven by electronhole recombination during PiN diode forward bias operation [2]. Generally, because the SF mimics the 3C-SiC (Eg=2.4 eV) crystal structure, its presence as an inclusion in 4H-SiC (Eg=3.2 eV) makes it electronically behave as a one-dimensional quantum well (QW) with carrier transport predominantly confined along the basal plane. Under such condition, the overall electronic properties of the crystal structure are fundamentally altered to the extent that the primary desired diode current conduction perpendicular to the basal plane is practically blocked, thereby severely d
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