Processor and System-on-Chip Simulation

Processor and System-on-Chip Simulation Edited by: Rainer Leupers Olivier Temam The current trend from monolithic processors to multicore and multiprocessor systems on chips (MPSoC) with tens of cores and gigascale integration makes hardware architecture

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Rainer Leupers · Olivier Temam Editors

Processor and System-on-Chip Simulation

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Editors Rainer Leupers RWTH Aachen Templergraben 55 52056 Aachen Germany [email protected]

Olivier Temam INRIA Saclay Batiment N Parc Club Universite rue Jean Rostand 91893 Orsay Cedex France [email protected]

ISBN 978-1-4419-6174-7 e-ISBN 978-1-4419-6175-4 DOI 10.1007/978-1-4419-6175-4 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2010933795 c Springer Science+Business Media, LLC 2010  All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper. Springer is part of Springer Science+Business Media (www.springer.com)

To Bettina (Rainer) and To Nathalie, Lisa, and Nina (Olivier).

Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Part I System Simulation and Exploration 2 The Life Cycle of a Virtual Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Kevin Smart

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3 Full-System Simulation from Embedded to High-Performance Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Jakob Engblom, Daniel Aarno, and Bengt Werner 4 Toward the Datacenter: Scaling Simulation Up and Out . . . . . . . . . . . 47 Eduardo Argollo, Ayose Falcón, Paolo Faraboschi, and Daniel Ortega 5 Modular ISA-Independent Full-System Simulation . . . . . . . . . . . . . . . 65 Gabriel Black, Nathan Binkert, Steven K. Reinhardt, and Ali Saidi 6 Structural Simulation for Architecture Exploration . . . . . . . . . . . . . . . 85 David August, Veerle Desmet, Sylvain Girbal, Daniel Gracia Pérez, and Olivier Temam Part II Fast Simulation 7 Accelerating Simulation with FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Michael Pellauer, Michael Adler, Angshuman Parashar, and Joel Emer 8 Scalable Simulation for MPSoC Software and Architectures . . . . . . . 127 Rainer Leupers, Stefan Kraemer, Lei Gao, and Christoph Schumacher vii

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Contents

9 Adaptive High-Speed Processor Simulation . . . . . . . . . . . . . . . . . . . . . . 145 Nigel Topham, Björn Franke, Daniel Jones, and Daniel Powell 10 Representative Sampling Using SimPoint . . . . . . . . . . . . . . . . . . . . . . . . 161 Greg Hamerly, Erez Perelman, Timothy Sherwood, and Brad Calder 11 Statistic

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