Properties of Point-Defects in Si for Process Modeling
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ABSTRACT The development of future Si device technologies will rely extensively on modeling, requiring truly predictive tools. Here we focus on the front-end processes, during which ionimplantation and annealing create 3-D impurity profiles that determine crucial electrical device parameters. The final configuration is the result of a complex interaction of dopant atoms with Si self-interstitials and vacancies, which themselves interact with each other as well as with the implantation-induced damage and interfaces. Predictive modeling requires for all these processes a solid understanding of the physical phenomena as well as accurate quantitative information. Si self-interstitials and vacancies are not observable directly in an experiment, but only via their interactions with some other physical quantity of the sample. We review our work employing dopant atoms in 6-doping superlattices (6-DSL) that yield directly the time averaged depth profiles of Si native point defects during a particular processing sequence. This approach is uniquely suited for giving insights into the interplay of point defects in Si, providing crosschecks for atomistic calculations as well as parameters for process simulators. We describe experiments to extract interstitial and vacancy parameters and discuss the influence of intrinsic and extrinsic interstitial traps, as well as of the annealing environment, on the native point defect population. The latter allows to place certain bounds on the interstitial vacancy recombination coefficient as well as the ratio of interstitial and vacancy equilibrium concentrations. INTRODUCTION The size of dynamic access memory (DRAM) chips is expectedIll to reach 64GBits per chip in the year 2010, a four-fold increase every three years (Fig. 1). By then the gate-length of the metal-oxide-semiconductor (MOS) transistors that make up such a chip will be 70 nm. With this increase in DRAM capacity of three orders of magnitude between present and 2010 there is a simultaneous drop in the price per bit (Fig. 1, squares and right ordinate) by about the same ratio. Traditionally, the path from a product specification to a finished product proceeds through several levels, as illustrated in Fig. 2. Each level hands over its output to the next, while relying on information about characteristic parameters from it. Logic design produces a schematic description of the product in terms of logic gates, registers and interconnections, while assuming that parameters such as clock-speed and -skew are within certain ranges guaranteed by the
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physical layout. The physical lay-out places the transistors, specifies the gate-length, etc., to achieve the target given by the logic design, using parameters such as threshold voltages, sheet resistances, and transit frequencies from the process design. Finally, process design casts the physical design targets into furnace temperatures and implant conditions, so that actual silicon can be processed. If after testing
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