Quality of Thermally Grown Oxides in 4H-SiC over Nitrogen or Phosphorus Implanted Regions
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Quality of Thermally Grown Oxides in 4H-SiC over Nitrogen or Phosphorus Implanted Regions
I. A. Khan, B. Um, M. Matin, M. A. Capano, & J. A. Cooper Jr. Electrical and Computer Engineering Department Purdue University, West Lafayette, IN 47906 USA ABSTRACT Current SiC metal-oxide-semiconductor-field-effect-transistors (MOSFETs) have regions of the gate electrode that overlaps the source/drain contact implant. The source/drain region is electrically isolated from this gate electrode extension by the gate insulator. Typically, the gate insulator is established through a controlled thermal oxidation step. The performance of the electrical isolation between the gate electrode and the source/drain implant region is studied using MOS systems for the nitrogen and phosphorus implant species. The dielectric strength of thermal oxide grown over a phosphorus implanted region is about four times lower than a non-implanted region and about two times lower than the nitrogen implanted region for the same implant and anneal conditions. INTRODUCTION Recent studies of the dielectric strength of thermally grown oxides on SiC reported in the literature have been over non-implanted epitaxial layers[1]. The oxide breakdown strength was measured to be about 10MV/cm at room temperature[1]. The electrical characteristics of the oxide specifically over implanted regions, however, have not been investigated extensively. Oxide quality over implanted regions is of special interest for SiC MOSFETs that have a gate electrode which overlaps the implanted source/drain regions. Such a gate overlap is inherent in a UMOSFET, as shown in Fig.1a, and in the case of a DMOSFET it is shown in Fig.1b. a)
Gate b) overlap region over implanted source
Gate overlap region over implanted
source
Source and Base Contact
Source and Base Contact N+/P+ doped Polysilicon gate
P+
N+
N+
P+ N+ P
P
N+ Gate Oxide
P N Gate Oxide
P N
N+/P+ Doped Polysilicon Gate
Drain contact
Drain contact
H5.16.1
Source and Base contact
Figure. 1. A schematic cross section of a a) UMOSFET and b) DMOSFET structure illustrating the gate overlap regions over the source contact implant. For n-channel MOSFETs, phosphorus and nitrogen are the preferred species for source/drain implantation[2]. The quality of the oxide over these regions can potentially affect the performance of the device. Low dielectric strength of the oxide can cause excessive gate leakage currents in the on-state, resulting in either total failure of the device or poor device transfer characteristics. Furthermore, excessive injection of carriers in these regions can significantly reduce the life of the device by creating a short between the source/drain and the gate. To study the dielectric strength of thermal oxides sandwiched between the gate electrode and the source/drain contact implant, MOS capacitors were fabricated on regions that had received a nitrogen or phosphorus implant. These capacitors were then characterized to determine the dielectric strength of the oxides. EXPERIMENT For the current exper
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