Recent Progress in Downsizing FeFETs for Fe-NAND Application

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Recent Progress in Downsizing FeFETs for Fe-NAND Application Le Van Hai, Mitsue Takahashi, Shigeki Sakai National Institute of Advanced Industrial Science and Technology Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki, 305-8568, Japan ABSTRACT Sub-micrometer ferroelectric-gate field-effect transistors (FeFETs) of 0.56 m and 0.50 m gate lengths were successfully fabricated for Fe-NAND cells. Gate stacks of the FeFETs were Pt/SrBi2Ta2O9(SBT)/Hf-Al-O/Si. The gate stacks were formed by electron beam lithography and inductively coupled plasma reactive ion etching (ICP-RIE). Ti and SiO2 hard masks were used for the 0.56 m- and 0.50 m-gate FeFETs, respectively, in the ICP-RIE process. Steep SBT sidewalls with the angle of 85° were obtained by using the SiO2 hard masks while 76° sidewalls were shown using Ti hard masks. All fabricated FeFETs showed good electrical characteristics. Drain current hysteresis showed larger memory windows than 0.95 V when the gate voltages were swung between 1±5 V. The FeFETs showed stable endurance behaviors over 108 program/erase cycles. Drain current retention properties of the FeFETs were good so that the drain current on/off ratios did not show practical changes after 3 days. INTRODUCTION Nowadays, flash memories have seen a high growth market, driven by the demand for various portable electronic appliances, like mobile phones and digital cameras. Floating-gate type (FG) NAND flash memories have played a key role and widely used in the products. However, the FG NAND will be no longer most suitable for high-performance non-volatile memory products like enterprise solid state drives which require low-power consumption and high reliability [1]. Ferroelectric-gate field-effect transistors (FeFETs) have attracted much attention as nonvolatile memory transistors [2-21]. Since a long data retention of an FeFET with Pt/SrBi2Ta2O9(SBT) /Hf-Al-O(HAO)/Si gate was achieved for the first time [5], we have made much progress in the FeFET fabrication process [5-10, 14,15,17-21]. We also have intensively studied the FeFET application to NAND (Fe-NAND) flash memories [6,19-21] because the FeFETs showed good characteristics such as long retentions, low operation voltages of 6 V and high endurance of 108 cycles for program/erase (P/E). The operation voltage is much lower and the endurance is much higher than those of the conventional FG NAND, which has 20V program voltage and 104 P/E cycles. Furthermore, the Fe-NAND flash memory has a good potential for scaling toward sub-10 nm, whereas the FG NAND flash memory is supposed to have intrinsic difficulty in downsizing to that scale [6]. In this study, we fabricated the Pt(250nm)/SBT(200nm)/HAO(7nm)/Si FeFETs and investigated their downsizing with keeping their good electrical properties. Electron-beam (EB) lithography and inductively coupled plasma reactive ion etching (ICP-RIE) using hard masks were key processes. We prepared two kinds of hard masks. One was a metal Ti hard mask made by a lift-off technique, the other was an insulator SiO2 hard mask by the ICP-RIE.

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