Reduction of hardware expenses in control unit with code sharing
- PDF / 196,673 Bytes
- 10 Pages / 594 x 792 pts Page_size
- 33 Downloads / 189 Views
REDUCTION OF HARDWARE EXPENSES IN CONTROL UNIT WITH CODE SHARING O. O. Barkalov,ab† L. A. Titarenko,bc and A. S. Lavrika
UDC 004.3
Abstract. A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%. Keywords: flowchart of algorithm, control unit, compositional microprogram control unit, code sharing, programmable logic devices of CPLD type, addressing of microcommands. INTRODUCTION Virtually any digital system includes the control unit (CU), which coordinates the interaction of system units [1]. The operation of the CU can often depend on the model of the digital automaton [2]. As a rule, in implementing the CU circuit, the problem of the reduction of hardware expenses arises [3]. The methods of the solution of this problem depend on the features of the control algorithm and element basis. For example, for a linear control algorithm, it is expedient to use the model of compositional microprogram control unit (CMCU) [4, 5]. In the present paper, we will implement a CMCU circuit in the basis of programmable logic chips (PLDs) of CPLD type (complex programmable logic devices) [6, 7]. Such PLDs consist of PML (programmable matrix logic) macrocells and interconnection matrices. A feature of PML is rather large number (several tens) of inputs and a limited number of terms [8, 9]. To reduce the number of macrocells in CU circuit, it is necessary to reduce the number of terms in the implemented functions. To this end, several sources of state codes can be used [10]. For CMCU, operator linear circuits (OLC) are used for the states. In the present paper, we propose the methods based on the application of several sources of OLC codes. The digital system control algorithm is represented as a linear flowchart of the algorithm (FCA) [1]. There are many digfferent models of CMCU [4], their choice is determined by the features of the FCA according to which the CU circuit is implemented. In what follows, we will consider a CMCU model with code sharing [4]. The proposed methods can be used for any CMCU model. BASIC CMCU MODEL WITH CODE SHARING Let a FCA G be represented by sets of nodes  and of arcs Å connecting these nodes. In this case, B = {b0 , bE } È B1 È B 2 , where b0 and bE are the initial and final nodes of the FCA, respectively; B1 is the set of operator vertices, | B1 | = M ; and B 2 is the set of conventional nodes. At the nodes bq Î B1 the sets of microoperations Y ( bq ) Í Y are written, where Y = { y1 ,... , y N } is the set of microoperations. At the nodes bq Î B 2 elements of the set of logical conditions are written, X = {x1 ,... , x L }. Let us introduce the definitions [4, 5] necessary for the further presentation.
a
Donetsk National Technical University, Donetsk, Ukraine, †A
Data Loading...
