Run-Time Adaptable Architectures for Heterogeneous Behavior Embedded Systems
As embedded applications are getting more complex, they are also demanding highly diverse computational capabilities. The majority of all previously proposed reconfigurable architectures targets static data stream oriented applications, optimizing very sp
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Universidade Federal do Rio Grande do Sul – Porto Alegre/Brazil 2 Delft University of Technology, Computer Engineering – Delft/The Netherlands {caco,mbrutzig}@inf.ufrgs.br, [email protected], [email protected]
Abstract. As embedded applications are getting more complex, they are also demanding highly diverse computational capabilities. The majority of all previously proposed reconfigurable architectures targets static data stream oriented applications, optimizing very specific computational kernels, corresponding to the typical embedded systems characteristics in the past. Modern embedded devices, however, impose totally new requirements. They are expected to support a wide variety of programs on a single platform. Besides getting more heterogeneous, these applications have very distinct behaviors. In this paper we explore this trend in more detail. First, we present a study about the behavioral difference of embedded applications based on the Mibench benchmark suite. Thereafter, we analyze the potential optimizations and constraints for two different run-time dynamic reconfigurable architectures with distinct programmability strategies: a fine-grain FPGA based accelerator and a coarse-grain array composed by ordinary functional units. Finally, we demonstrate that reconfigurable systems that are focused to single data stream behavior may not suffice anymore.
1 Introduction While the number of embedded systems continues to grow, new and different devices, like cellular phones, mp3 players and digital cameras keep appearing on the market. Moreover, a new trend can be observed: the multi-functional embedded system, which performs a wide range of different applications with diverse behaviors, e.g. present day portable phones or PDAs. As a consequence, simple general purpose or DSP processors cannot handle the additional computational power required by these devices anymore. Although a large number of techniques that can solve the performance problem are available, they mainly exploit the instruction level parallelism (ILP) intrinsic to the application, e.g. the superscalar architectures. However, these architectures spend a considerable amount of power while finding the ILP [1]. For that reason, alternative approaches, such as reconfigurable fabrics, have been gaining importance in the embedded domain, speeding up critical parts of data stream oriented programs. By translating a sequence of operations into a hardware circuit performing the same computation, one could speed up the system and reduce energy consumption significantly [2]. This is done at the price of additional silicon area, exactly the resource mostly available in new technology generations. R. Woods et al. (Eds.): ARC 2008, LNCS 4943, pp. 111–124, 2008. © Springer-Verlag Berlin Heidelberg 2008
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A.C.S. Beck et al.
Recent FPGA based reconfigurable devices targeting embedded systems are designed to handle very data intensive or streaming workloads. This means that the main design strategy is to consider the target applications as havin
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