Selective Epitaxial Growth of Strained Silicon-Germanium Films in Tubular Hot-Wall Low Pressure Chemical Vapor Depositio
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wafers were cleaned using a piranha cleaning procedure again, followed by a 5 second BHF dip and a thorough deionized water rinse, prior to being loaded into the hot-wall reactor. The capability of growing quality Si SEG was first demonstrated in the system [3]. For Si SEG, the typical growth conditions studied were 900-950 'C, 0.75 Torr, and flow rates of 25 and 500 sccm for DCS and H2 , respectively. Then the SiGe SEG followed based on the process flow as determined from Si SEG. The typical SiGe SEG conditions were 650-800 'C, 0.8 Torr, with flow rates of DCS and H2 of 27 and 750 sccm, respectively. GeH 4 (9% in H 2) flow rate was varied between 20 and 50 sccm. However, several process improvements were found to be needed and were implemented in chganging from Si SEG to high quality SiGe SEG. Figure 1 outlines the typical process temperature profiles of the experiments for Si and SiGe SEG. The process improvements are discussed in the next section. 1000 -1
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Figure 1.LPCVD reactor temperature profiles used for the selective epitaxial growth of Si (a) and Si~e (b). Steps in (a): 1. Load wafers, N2 purge; 2. H2 bake; 3. Si SEC; 4. N2 purge; and 5. Unload wafers. Steps in (b): 1. N2 purge; 2. H2 bake; 3. Si deposition; 4. N2 purge, load wafers; 5. H2 bake; 6. SEC buffer layer of Si; 7. Si~e SEC; and 8. N2 purge, unload wafers. PROCESS IMPROVEMENTS Two-Step Hydrogen Bake
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Ce Outgassing
The hydrogen bake conditions used for Si SEC in the reactor of this study were T=950 TC and P=0.9 Torr for 30 minutes. They resulted in a good initial growth surface and good electronic quality was achieved [3]. However, these hydrogen bake conditions were found to be ineffective for Si~e SEC growth. Substrate surface was contaminated by Ce particles after the hydrogen bake as observed by scanning electron microscopy (SEM) and energy dispersive spectroscopy (EDS) analysis [4]. Thermodynamic analyses revealed that Ce outgasses at conditions of high temperature and low pressure [4]. Because the system had hot-walls, there was deposition of Si~e on the reactor wall from previous runs. The deposition on the wall thus provided a Ce source for Ce outgassing. Therefore, fundamental knowledge-driven modifications in the hydrogen bake process were devised and adopted. A hydrogen bake of the empty reactor at 1000 'C, in 0.75 Torr of flowing hydrogen for 1 hour prior to substrate wafer insertion was found to significantly improve the quality of the Si~e SEC films later on. These conditions favored high Ce/Si ratios in the gas phase, and Ce from the deposits on the reactor wall thus entered the gas phase was carried away by the H2 . After this bake, a DCS flow was introduced at the same conditions for 10 minutes. This resulted in a thin Si film over everything in the reactor, thus 266
further reducing the possibility of Ge outgassing, if any was left. A N2 purge and loading of the wafers were then done followed immediately by a secon
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