Solution Processable Nanowire Field-Effect Transistors
- PDF / 544,967 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 88 Downloads / 207 Views
Solution Processable Nanowire Field-Effect Transistors
Charles Opoku1, Lichun Chen2, Frank Meyer2, Maxim Shkunov1 1 2
Advanced Technology Institute, University of Surrey, Guildford, GU2 7HX, UK Merck Chemicals, Chilworth Technical Centre, Southampton, SO16 7QD, UK
ABSTRACT Hybrid field-effect-transistors (FETs) with germanium nanowire (NW) arrays and organic gate dielectric are presented. The nanowire deposition steps are fully compatible with printed electronics route. NW FETs demonstrate good performance with On/Off ratios of ~103 and hole mobilities of ~13 cm2/Vs in both nitrogen and air atmosphere. These results suggest that the hybrid nanowire FETs could be used in large area inexpensive electronics. INTRODUCTION Fabrication of field-effect transistors using semiconducting ‘inks’ at low temperatures and on a large area substrates could potentially give rise to low-cost and disposable electronics that can also be lightweight and flexible if produced on plastics substrates. The solution processability of such devices is making them even more attractive since they can be printed without the need for high vacuum techniques and energy-demanding high temperature fabrication steps. Recently a number of principle approaches including organic semiconductors [1], amorphous silicon (a-Si) [2], solution processable semiconducting oxides[3, 4], and semiconducting carbon nanotubes[5] have been undertaken for large area printable, flexible transistors. All of them had some challenges, hampering their applications for high-performance solution-processable printable transistors, either due to mobility limitations of about 1 cm2/Vs (organics and a-Si) or high temperature processing (oxides) and purification drawbacks (single wall carbon nanotubes). Semiconducting nanowire materials are offering a potential breakthrough in the area of high performance printable transistors. Inorganic nanowires maintain most of the bulk single crystal properties, including semiconducting behavior, crystal lattice structure, and efficient charge transport irrespective of nanowire diameter. The synthesis of nanowires can be completely separated from device fabrication thus allowing two-fold advantage. Firstly, controlled growth of nanowires can be tailored to produce high-quality single-crystal structures with a desired length-to-width ratio; secondly, these nanomaterials may be formulated into ‘inks’ for selective low-temperature additive deposition on substrates. If the alignment of these nanowires upon deposition can be controlled to ‘bridge’ device electrodes, then device performance per nanowire is expected to be comparable to that of traditional single-crystal semiconductor technology. Clear advantages of nanowire approach are the ease of processing, wide prospects for self-assembly ‘bottom-up’ fabrication, compatibility with plastic substrates, and also possibility for fast device prototyping based on additive printing technology.
Currently there have been no reports on using single crystalline germanium nanowire arrays for top-gate conf
Data Loading...
