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0936-L11-03

Spin-on Gate Dielectric Materials for Next Generation Display Systems Jinghong Chen1, Mehari Stifanos1, Jan Nedbal1, Ahila Krishnamoorthy1, Emma Brouk1, Pete Smith2, and Brian Daniels1 1 Dielectrics, Honeywell Electronic Materials, 1349 Moffett Park Drive, Sunnyvale, CA, 94089 2 Honeywell Specialty Materials, 101 Columbia Road, Morristown, NJ, 07962

ABSTRACT We present recent advances on spin-on polymers as gate dielectric for thin film transistors. We have developed a siloxane film type I with significantly improved dielectric properties. At a curing temperature of 250 ˚C, the dielectric constant is 3.46, the breakdown voltage is 4.10 MV/cm at 1 µA/cm2, the leakage current is 4.9 x 10-8 A/cm2 at 2.5 MV/cm, and the CV hysteresis is 3.4 V. At a curing temperature of 425 ˚C, the dielectric constant, the breakdown voltage, the leakage current, and the CV hysteresis are 3.2, 4.73 MV/cm, 2.6 x 10-8 A/cm2, and 0.44 V respectively. INTRODUCTION The fabrication of thin film transistors (TFTs) requires the deposition of light transmissive dielectric materials as planarization layers, gate dielectrics, and interlayer dielectrics. A typical bottom gate TFT is shown in Figure 1. Currently, these passivation layers in TFT structures are SiNx or SiO2 deposited by plasma enhanced chemical vapor deposition (PECVD). However, there is a technology shift from CVD to spin-on dielectrics due to the need to reduce cost in large panel manufacturing and to improve performance in mobile displays. Since the size of the mother glass keeps increasing, the capital investment of large size CVD tools will become prohibitive. Solution processes offer a cost effective alternatives. In addition, a solution process is a non-conformal coating method offering good planarization. It has been proven that better planarization of the TFT will result in improved aperture ratio, thus improving light utilization efficiency of displays [1].

Planarization Layer

Planarization Layer

Gate Dielectric Gate

Glass

Figure 1. Cross section of bottom gate TFT structure.

Spin-on dielectric materials based on silicates or siloxanes are prepared by a sol-gel method [2]. For Gate Dielectric (GD) applications, residual silanol content, absorbed moisture, mobile ions from solvents and residual additives are all potential sources of defects in the bulk and at the interface between the GD and the semiconductor. As a result, spin-on dielectrics exhibit insufficient dielectric properties compared to the thermal oxide which is used in semiconductor Field Effect Transistor (FET) and CVD SiNx or SiO2 in current TFTs. In this paper, we present spin-on polymer film type I with significantly improved dielectric properties. EXPERIMENT Spin-on polymer type I was made from a standard sol-gel method through an acid/base catalyzed hydrolysis and condensation process. Type I sols were spin-coated on p-Si wafers, baked on a coater at different conditions, and cured in a furnace at various temperatures in N2 flow for one hour [3]. The thermal stability of additive C was det