State-of-the-Art

In this chapter, the related work of this book is elaborated. Initially, fault injection techniques are discussed. Following that, major high-level reliability estimation techniques are briefly illustrated.

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State-of-the-Art

In this chapter, the related work of this book is elaborated. Initially, fault injection techniques are discussed. Following that, major high-level reliability estimation techniques are briefly illustrated. Afterward, traditional and state-of-the-art architectural fault tolerant techniques are selectively presented. Finally, several design approaches to enhance system-level reliability are explained.

3.1 Fault Injection and Simulation Fault injection (FI) has been applied over several decades to validate the device dependability under faulty conditions. The benefits of FI include but are not limited to the following: • Track the propagation of faults and their consequences in the system. • Verify the system behavior under a tolerated range of faults, which is documented in the device specification. • Explore efficient fault tolerant techniques in a specific faulty environment. • Estimate fault coverage of testing mechanism in the device. • Understand the behavior of real physical faults and benchmark with high-level fault injection techniques. Hardware related FI techniques are the focus of this book. According to their implementation mechanism, FI techniques are classified into physical FI, simulated FI and emulated FI. A survey of techniques from individual domain follows in this section.

© Springer Science+Business Media Singapore 2018 Z. Wang and A. Chattopadhyay, High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip, Computer Architecture and Design Methodologies, DOI 10.1007/978-981-10-1073-6_3

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3 State-of-the-Art

3.1.1 Physical Fault Injection Physical FI or hardware FI involves the fault injection using physical sources such as neutron flux or through processor pins. Physical FI can be further classified into contact technique and non-contact technique. The contact technique usually uses pins as the inputs of faults, which can only test selective faults. The non-contact technique involves no direct contact with the source of faults, such as radiation rays, so that the injection location can spread over the device. The physical FI techniques are very fast in speed and able to accurately model low-level faults. The major disadvantages are the large setup cost, low controllability, and observability. Representative physical FI tools are listed in the following. • MESSALINE [8] adopts both active probes and sockets to inject faults through pins of device. It is able to inject multiple fault types including stuck-at, bridging, and open faults, while can also control the duration of faults. The injection module can select up to 32 injection points. Test sequences are automatically generated by a manager module, which also performs fault analysis. • RIFLE [124] presents a pin-level FI tool for processor architectures. It is based on the idea of trigger and tracing, which records extensive behavioral information after faults. No feedback circuits are needed for the mismatch detection. RIFLE focuses on its ability for fault analysis, which has been appl

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