Study of PZT Film Stress in Multilayer Structures for MEMS Devices
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287 Mat. Res. Soc. Symp. Proc. Vol. 605 © 2000 Materials Research Society
furnace annealing was studied by annealing the Si/Dielectric/Pt stack at 700'C in RTA, 60 sec, as well as in furnace @15°C/min ramp rate. Tencor FLX-2908 system was used to measure the changes in the radius of curvature of the substrate caused by deposition of the films. Measured negative values for stress indicated a compressive stress and positive ones a tensile stress. We utilized the in-situ heating capability of the system to perform the furnace annealing and stress measurement. RESULTS AND DISCUSSION OF STRESS MEASUREMENTS Measured stress data were mainly categorized in four groups. The first group, reported in sectionl below, consisted of measured stress on the Si0 2 and Si3N4 films having different thickness, Pt deposited on the dielectric (as-deposited, as well as RTA annealed) films, RTA of the deposited bottom Pt, spin-coated PZT film (500 nm) on the bottom Pt, deposition of Pt on the PZT, and RTA of the top Pt. The second group of the measured data (section 2) was related the different thickness of the PZT films on a platinized substrate having a fixed (600 nm) SiO 2 film thickness. The third group data (section 3) was taken with incremental increases of 250 nm PZT films on two different types of platinized substrates, one having Si0 2 (700 nm), and the other Si 3N4 (300 nm) films under the bottom Pt layer. The fourth group data (section 4) was obtained after annealing the platinized substrates separately in furnace and RTA followed by PZT deposition on both. L.a. Si/Dielectric/Pt stack: Stress was measured on a Si/Dielectric/Pt stack with several dielectric layer (Si0 2 , Si 3N4) thicknesses at various stages of deposition and annealing. The results are shown in table 1. Stress due to deposition of bottom Pt films on as-deposited Si0 2 did not change appreciably, while it increased compressively for Si 3N4 as show in table 1. But in all cases the stress changed to tensile and increased to over 1000 MPa after annealing the stack in RTA at 700'C. This is due to film recrystallization during annealing. After cooling to room temperature, a large tensile stress developed due to the larger thermal expansion of Pt compared to Si [6]. Table 1. Stress of the (Si/ Dielectric/Pt) stack at various stages with as-deposited dielectric layers.
Stress (MPa) 1.Dielectric as-deposited 2. Pt-bottom as-deposited 3. RTA(700°C)
SiO 2 thickness (nm) 250 600 700
Si3 N4 thickness (nm)
155
300
-400 -425 1001
-88 -311 1190
-201 -380 1260
-450 -455 1100
-460 -465 1145
Effect of annealing of as-deposited dielectric films, before Pt deposition, was also investigated. The as-deposited (Si/Dielectric) stacks were RTA at 700'C followed by Pt
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deposition and RTA at 700'C. Stress measurements on these stacks at various stages of deposition and annealing are shown in table 2. Measured stress changed from compressive to tensile upon annealing of both Si0 2 and Si3N 4 layers. Annealing of Si0 2 eliminates micropours in the film that accommodate water
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