Super high-dielectric-constant oxide films for next-generation nanoelectronics and supercapacitors for energy storage

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oduction The microelectronics revolution of the 20th century was based on silicon (Si) as the electronic material, due to its exceptional electrical properties, with the superior SiO2 insulator integrated with Si. Complementary metal oxide semiconductor (CMOS) transistors, the cornerstone of the Si-IC (integrated circuit) technology, have been continuously scaled down in size to achieve faster, cheaper, and more energy-efficient microelectronics, including electrically erasable programmable read-only memory , also named “FLASH,” and dynamic random-access memory (DRAM), addressing multibillion-dollar markets. However, new generations of Si-based nanoscale CMOS devices still need novel materials, materials integration, processing, and device architecture beyond the pure Si-based technology. In this sense, the technology roadmap1 for nanoscale

CMOS devices, in the 1990s and early 2000s, indicated that an equivalent oxide thickness (EOT) of a high-k dielectric layer with a real thickness equivalent to SiO2 < 1.0 nm of the SiO2 CMOS gate was needed to maintain a suitable capacitance when the width of the CMOS gate was 1.0 nm and further allowing the reduction of the capacitor area A, as indicated by the parallel plate capacitance equation (C = εο k A/t), where k is the dielectric constant, t = thickness of the gate dielectric layer,

Orlando Auciello, The University of Texas at Dallas, USA; [email protected] Geunhee Lee, BTI Solutions, dba Blue Telecom Inc., USA; [email protected] Chunya Wu, The University of Texas at Dallas, USA; [email protected] Yuanning Chen, MicroSol Technologies Inc., USA; [email protected] Jesus J. Alcantar-Peña, Microtechnologies Division, Center for Engineering and Industrial Development, Mexico; [email protected] Israel Mejia, Microtechnologies Division, Center for Engineering and Industrial Development, Mexico; [email protected] Elida de Obaldía, Universidad Tecnológica de Panamá, Republic of Panamá; [email protected] doi:10.1557/mrs.2020.67

© 2020 Materials Research Society BULLETIN •Core VOLUME 45of• use, MARCH 2020 • at mrs.org/bulletin Downloaded from https://www.cambridge.org/core. Uppsala Universitetsbibliotek, on 11 Mar 2020 at 16:52:22, subject to MRS the Cambridge terms available https://www.cambridge.org/core/terms. https://doi.org/10.1557/mrs.2020.67

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SUPER HIGH-K DIELECTRIC OXIDE FILMS

Figure 1.  (a) Schematic of a complementary-metal oxide semiconductor (CMOS) transistor showing the key gate dielectric layer controlling motion of electrons from source to drain, through the gate dielectric/Si substrate interface, when a voltage is applied on the metal gate dielectric contact (for SiO2 ≤1 nm thickness, electrons (e–) would tunnel through the SiO2 into the gate electrode, rendering the CMOS transistor useless). (b) High-resolution transmission electron microscope (HRTEM) cross-sectional image of a CMOS transistor with a SiO2 layer, with the limiting thickness that required replacement of SiO2 with a high-k dielectric m

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