Surface states in a monolayer MoS 2 transistor
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In this article, we have explored the interface states that form between the channel of a monolayer MoS2 transistor and a high-j gate dielectric. These interface states lead to large hysteresis in the drain current versus gate voltage characteristic or the so-called transfer characteristic of the transistor. By applying carefully designed pulses to the gate of the transistor, we show that it is possible to both understand the nature of the interface states and minimize the hysteresis, so that the transfer characteristic can be reliably used for subsequent extraction of material parameters such as mobility.
The transition metal dichalcogenides (TMDs) have recently garnered much attention due to their potential for new and highly efficient electrical and optical devices.1–11 Unlike graphene,2 TMDs have a finite band gap.3 This is critical for transistor applications and indeed excellent switching behavior with high ON/OFF ratio has been demonstrated for a number of different TMDs. A three terminal transistor behavior is also used extensively to probe the material properties, such as dielectric permittivity and mobility, of the TMD material. However, when these structures are characterized in the ambient conditions, different molecules, such as oxygen, water vapor, etc., can get absorbed at the interface between the channel and the gate oxide. These molecules typically lead to trapping centers at the interface.12–17 As a result, in almost all experiments a DC sweep of the gate voltage, Vg, shows large hysteresis of the drain current, ID. These trap states and resulting hysteresis are highly undesirable. For example, the traps can continuously change the threshold voltage as a function of gate bias; more importantly they can significantly reduce the ON current. On the other hand, the two branches of the hysteresis curves are typically different and usually depend on the initial condition, rate of sweep, etc. Therefore, critical parameters, such as mobility, which is extracted from the slope of the Id–Vg characteristic (or the so-called transfer characteristics), can no longer be reliably estimated. In this work, we first show that the dependence of the hysteresis on different parameters can be effectively exploited to quantify the nature and density of the trap states. Such information can provide important insight as to how to engineer the interface for optimum device performance. Next, we show that by applying Contributing Editor: Jeremy T. Robinson a) Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/jmr.2015.405 J. Mater. Res., Vol. 31, No. 7, Apr 14, 2016
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carefully designed pulses to the gate of the transistor, the effect of the trap states can be completely removed and thus the hysteresis can be eliminated, revealing the intrinsic nature of the material itself. In this work, we have used a monolayer MoS2 as our model system. Aluminum dioxide (Al2O3) was used as the gate dielectric and was deposited using the atomic layer depos
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