The Dependence of Poly-Si TFT Characteristics on the Relative Misorientation Between Grain Boundaries and the Active Cha
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The Dependence of Poly-Si TFT Characteristics on the Relative Misorientation Between Grain Boundaries and the Active Channel Y.H. Jung, J.M. Yoon, M.S. Yang, W.K. Park, H.S. Soh, Anyang Laboratory, LG-Philips LCD Co. Ltd, Dongan-gu, Anyang-shi, Kyungki-do, KOREA; H.S. Cho, A.B. Limanov, and J.S. Im, Program in Materials Science, Columbia University, New York, NY 10027 ABSTRACT We present device-related experimental results that quantitatively reveal the effect of varying the active channel/grain-boundary misorientation on the resulting TFT characteristics. Specifically, using low-temperature SLS processes, we have fabricated and analyzed n-channel and p-channel devices (40 µm width x 8 µm length) with three different orientations of the channel with respect to the grain boundaries: parallel, 45° inclined, and perpendicular on Corning 1737 glass substrates. The results reveal that the TFTs with the best (worst) characteristics were obtained for the devices with parallel (perpendicular) alignment. In general, for both n- and p-channel devices, the most prominent orientation-dependent effects were observed in the values of the field effect mobilities, which were 340, 227, and 141 cm2/Vsec for n-channel devices and 145, 105, and 80 cm2/Vsec for p-channel devices, in the order of increasing orientation mismatch. In contrast, no notable effect was manifested in the leakage currents, while small effects were seen for the subthreshold slopes and threshold voltages. The degradation of device performance under hotcarrier stress was found to decrease with increasing orientation mismatch. INTRODUCTION Integration of TFT-LCD panels by fabricating the gate driver and data driver circuits onto the same thin Si film on an insulating substrate demands higher TFT device performance than is available with conventional ELA-processed poly-Si TFTs. The channel mobility for poly-Si TFTs fabricated on films crystallized using conventional ELA methods is ∼140 cm2/Vsec for nchannel devices and ∼60 cm2/Vsec for p-channel devices, values that are insufficient for the operation of driver circuits, restricting the use of TFTs for those devices. The first step in improving device performance in TFTs is to improve the quality of the Si thin film. For poly-Si TFTs, the electrical properties of the device are limited by the presence of grain boundaries in the channel region. In particular, channel mobility is limited by the formation of potential barriers at the grain boundaries, which are the result of trapping states due to dangling bonds [1]. Therefore, improvement in electrical properties of polycrystalline Si thin films can be achieved by reducing the number of grain-boundaries and by controlling their location within the channel region [2]. The Sequential Lateral Solidification (SLS) method [3-6] has been developed to achieve this goal by controlling the location and orientation of grain boundaries or by eliminating grain boundaries in the channel region altogether. For example, the directional solidification form of SLS produces material with
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