The Effects of Surface Treatments for Low Temperature Silicon Dioxide Deposition on Cadmium Telluride.
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THE EFFECTS OF SURFACE TREATMENTS FOR LOW TEMPERATURE SILICON DIOXIDE DEPOSITION ON CADMIUM TELLURIDE.
Seong S. Choi, S. S. Kim, D.V. Tsu and G. Lucovsky, Departments of Physics and Materials Science and Engineering, North Carolina State University, Raleigh, N.C. 27695-8202
Abstract We have successfully deposited thin films of Si02 on a cadmium telluride substrate at low temperature (Ts =100*C-300°C) by remote plasma enhanced chemical vapor deposition (Remote PECVD). The native oxide on the CdTe substrate has been removed, prior to deposition by either chemical etching in methanol and 1% bromine, or by dissolution in deionized water. After removal of the native oxide, the CdTe was inserted into a UHV-compatible deposition chamber and a He+ plasma treatment was performed prior to deposition of an SiO 2 film. This treatment promotes strong adhesion between the deposited SiO2 film and the CdTe surface. We find that the initial oxide removal process does not influence Si0 2 adhesion. The effect of the He+ plasma treatment on the CdTe surface has been studied by Auger electron spectroscopy(AES), and Reflection high energy electron diffraction (RHEED). Introduction There is considerable interest in the formation of device structures that incorporate both CdTe and (Hg,Cd)Te layers. The majority of the proposed device structures also will require either surface passivation of junction boundaries, or the use of dielectric films as gate insulators in field effect transistor(FET) heterostructures. Many previous studies [1-3] have identified problems related to the adhesion of low temperature Si0 2 films onto CdTe surfaces. The maximum temperature to which CdTe surfaces can be exposed, without significant disproportionation is about 340*C. It has been suggested that this problem derives from a chemically inert CdTe surface state [4-6,8,10]. To circumvent this problem, alternative dielectric materials have been considered, e.g., the wide-band-gap 1I-VI material ZnS [2]; however, the intrinsic resistivity of this material, and the quality of the thin films of ZnS generated by low temperature processes are not sufficient for many applications [2]. Therefore we have concentrated our effort on the CdTe surface processing prior to low temperature Si0 2 deposition. Experimental
Procedures
Substrates of cadmium telluride were obtained from Santa Barbara Research Corporation (SBRC). The substrates were prepared by an initial degreasing in trichloroethylene(TCE), acetone, and methanol. This was followed by removing the native oxide by either dissolution in deionized (D.I.) water (at least 30 minutes is required) [5], or by chemical etching in a 1% bromine/methanol solution [6,7]. After either of these processes, the sample was immediately inserted into a UHV multichamber surface process/surface analysis/dielectric deposition system [9] to minimize reoxidation and/or surface contamination. Upon introduction into the system, the substrates were first examined for chemical purity and stoichiometry by AES. The substrates were then annea
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