The Integration of the Ferromagnetic Inductors into the Standard CMOS Chip
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The Integration of the Ferromagnetic Inductors into the Standard CMOS Chip Oleg Nizhnik1, Olinver M. Vinluan1, Kohei Higuchi1, Koji Sonoda1,2, Masatoshi Ishii1,2, Kazusuke Maenaka1,2 1 Maenaka Human-Sensing Fusion Project, Japan Science and Technology Agency, Open Labs., Bldg, University Of Hyogo 2167 Shosha, Himeji, Hyogo, 671-2280, Japan 2 Graduate School of Engineering, University of Hyogo, 2167 Shosha, Himeji, Hyogo, 671-2280, Japan ABSTRACT An inductor in standard CMOS process having an inductance of 52 nH and a quality factor of 1.5 at frequency equal to 80 Mhz was fabricated. The polymer passivation layer of the standard CMOS inductor was etched out. The silicon substrate under the inductor, having a thickness of 280 μm was also etched out by deep reactive ion etching (DRIE). Ferrite material ZnFe2O4 and amorphous material Fe4.7Co70.3Si15B10 was then sputtered on top of the inductor sequentially. The same sputtering procedure was also performed into the bottom of the inductor. The result is an inductor that is sandwiched by multiple ferromagnetic layers. The inductance of the new ferromagnetic inductor has increased by 15% from 52 nH to 60 nH. The quality factor has also increased by 20% from 1.5 to 1.8. INTRODUCTION Monolithic DC-DC buck converters are very attractive for portable electronic devices because the usually bulky off-chip passive (inductor and capacitor) components are replaced by on-chip passive components. Using on-chip passive components will result in the reduction of size, cost and weight of these portable electronic devices. The disadvantage of using on-chip aircore inductors is their very low inductance density (80nH/mm2). Significant amount of die area (30% in 0.18 μm in SoC and 50% in 90 nm SoC) is consumed to achieve an inductance of tens of nano-Henries (nH). If inductor with low inductance (
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