Transforming Signal Processing Applications into Parallel Implementations
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Editorial Transforming Signal Processing Applications into Parallel Implementations Ed F. Deprettre,1 Roger Woods,2 Ingrid Verbauwhede,3 and Erwin de Kock4 1 Leiden
Embedded Research Center, Leiden University, Niels Bohrweg 1, 2333 CA Leiden, The Netherlands of Electronics, Electrical Engineering and Computer Science, ECIT Institute, Queens Island, Queens Road, BT3 9DT Belfast, Ireland 3 Katholieke Universiteit Leuven, ESAT-COSIC, Kasteelpark Arenberg 10, 3001 Leuven, Belgium 4 NXP Semiconductors, High Tech Campus 46, 5656 AE Eindhoven, The Netherlands 2 School
Received 9 August 2007; Accepted 9 August 2007 Copyright © 2007 Ed F. Deprettre et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Improving silicon technology has offered the possibility of heterogeneous platforms involving multiple multiprocessors, DSP processors, and FPGAs, but the key issue is the creation of the methodologies and tools that allow designers to quick and efficient map complex DSP systems onto such platforms. Typically, these design processes will involve application modeling and development of transformations for mapping these application models onto hardware architecture models against some key performance criteria such as timing, area, or power consumption. The purpose of this special issue is to highlight work which addresses the limitations in mapping from the application model onto the architecture model for complex DSP systems. These are not addressed in current design tool offerings to any great extent and issues include automatic translation of features in application specific models such as tokens and actors into “architecture model” specific expressions; exploration of algorithmic parallelism in such a way to make it match hardware platforms and development of transformations to reduce energy consumption and area against a throughput budget. The papers addresses a number of topics ranging from model of computation (MoC) representations through to tools to explore realizations from SystemC descriptions. In “SPRINT: a tool to generate concurrent transaction level models from sequential code,” J. Cockx et al. describe a tool to generate a concurrent SystemC transaction level model from sequential code. Using this tool, different parallelization alternatives were evaluated during the design of an MPEG-4 simple profile encoder and an embedded zero tree coder. With their approach, generation was carried out
in minutes thereby allowing extensive exploration of the design space. In “Self-timed scheduling analysis for real-time applications,” O. M. Moreira and M. J. G. Bekooij describe an approach that uses multirate dataflow graphs (MRDFs) to schedule the tasks of a hard real-time streaming application onto a multiprocessor system-on-chip. They extended the temporal analysis of self-time scheduling (STS) for MRDF graphs to model not only the average throughput but laten
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