Transient Current and Transient Capacitance Measurements of Defects in AlGaAs Hemts
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TRANSIENT CURRENT AND TRANSIENT CAPACITANCE MEASUREMENTS OF DEFECTS IN ALGAAS HEMTS R. Magno and R. Shelby, Naval Research Laboratory, Washington, DC 20375 ABSTRACT The defects present in AlGaAs high electron mobility transistor (HEMT) devices subjected to accelerated lifetime tests have been studied by transient current, and when possible, by transient capacitance techniques. By measuring transient source-drain currents following the application of a voltage pulse to the gate it is possible to perform deep level transient spectroscopy (DLTS) experiments on HEMT devices which are too small for the conventional capacitance DLTS. The capacitance and current spectra for both stressed and unstressed HEMTs contain the AlGaAs DX defect. The current DLTS spectra for stressed devices contain an additional feature which is not found in capacitance DLTS measurements on the stressed HEMTs. This additional current DLTS feature is anomalous in that the transient has a sign which is opposite to that expected for a majority carrier trap. The absence of the new defect in the capacitance DLTS suggests that the defect is located in the channel between the gate and either the source or the drain. The current DLTS line shape of the stressed induced defect depends upon the polarity and size of the source-drain voltage. INTRODUCTION Deep level transient spectroscopy (DLTS) techniques are being investigated as a method for studying process induced or lifetime stress induced defects in high electron mobility transistor (HEMT) devices.[1] Because state of the art devices have gate lengths less than 0.3 ýiLm their areas are too small for the usual capacitance DLTS techniques. An alternate approach is to monitor the transient source-drain current following the application of a defect filling bias pulse to the gate. The current transients are measured as the temperature of the device is swept over a range where the defects have a reasonable emission rate. These procedures are similar to those used in capacitance DLTS where a capacitance transient is monitored while sweeping the temperature.[2] Current DLTS is more difficult to interpret than capacitance DLTS because the source-drain current depends on the mobility and geometry of the conducting channel, as well as the carrier concentration. The source-drain voltage, VDS, is an additional parameter which is not available in capacitance DLTS. The sensitivity of current DLTS line shapes to the size and polarity of VDS, is the subject of this study. Because VDS makes the potential under the gate nonuniform, it may be possible to profile the defects under the gate by varying the size and polarity of VDS. Since a model for current DLTS line shapes is not available, the results presented here can only be discussed in a qualitative manner. Current DLTS has been used by a number of research groups to study metalsemiconductor field-effect transistors (MESFET)[3,4], to examine the DX center[5] in AIGaAs HEMTs[5,6,7], and to study the results of accelerated lifetime stress tests in HEMTs[l]. In the curre
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