Trench and Via Filling with Electroplated Copper: Effect of Current Density and Pulse Waveform
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TRENCH AND VIA FILLING WITH ELECTROPLATED COPPER: EFFECT OF CURRENT DENSITY AND PULSE WAVEFORM 1
C. H. Seah, 2S. Mridha, 2Y. K. Siew, 2G. Sarkar and 3L. H. Chan 1 Thin Film Dept., Chartered Silicon Partners Pte Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406, Singapore Phone/Fax: (65)-3946348/3946516, Email: [email protected] 2 School of Applied Science, Nanyang Technological University, Nanyang Avenue, Singapore 639798, Singapore 3 Research & Development Dept., Chartered Semiconductor Manufacturing Ltd., 60 Woodlands Industrial Park D, Street 2, Singapore 738406, Singapore ABSTRACT A study was carried out to investigate the effect of current density and pulse waveform on the filling of line trenches and contact vias with aspect ratio of 2:1 for sub-0.25 µm device manufacturing using normal pulse plating of copper. The growth pattern of the copper films deposited using 0.05 and 0.10 A/cm2 current density gave no significant difference. Small grains were seen to have nucleated uniformly across the line trenches and via holes after 1 second of electroplating. With increasing the deposition time to 2 seconds, a slight buildup of the film thickness was observed in both trenches and vias without significant increase in the size of the copper grains. Grain growth involving the coalescence of small grains occurred after 5 seconds of plating and a further buildup in thickness and fill up of the trenches and vias occurred after 10 seconds of deposition. When the patterned wafers were plated with a pulse waveform of 3 ms on and 0.5 ms off, the filling of trenches could not be complete after 30 seconds of electroplating. A complete filling of the trenches was achieved within 30 seconds of deposition using a pulse waveform of 6 to 8 ms on and 1 to 2 ms off. When the on-period was increased above this range to 9.9 ms, voids were observed at the centre of the via holes. INTRODUCTION Electroplating has become the technology of choice for the first generation of copper dual damascene interconnects used for fabricating advanced CMOS devices [1-2] because of its relatively low cost, high deposition rates and ease of filling high aspect ratio features. Successful electrochemical deposition of copper into trenches lined with copper seed and diffusion barrier, produced film resistivity of
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