Tuning lattice thermal conductance in ultra-scaled hollow SiNW: Role of porosity size, density and distribution
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Tuning lattice thermal conductance in ultra-scaled hollow SiNW: Role of porosity size, density and distribution Abhijeet Paul*, Kai Miao, Mathieu Luisier, and Gerhard Klimeck School of Electrical and Computer Engineering, Network for Computational Nanotechnology, Purdue University, West Lafayette, IN, 47907, USA. Email: [email protected] ABSTRACT Porous crystalline Si nanowires (PC-SiNW) represent an attractive solution for enhancing the thermoelectric efficiency (ZT) of SiNWs by reducing the lattice thermal conductance (κl). A modified valence force field (MVFF) phonon model along with Landauer’s approach is used to analyze the ballistic κl in PC-SiNWs. A systematic study focusing on the influence of pore size, density, and distribution on the ballistic κl of PC-SiNWs is presented. The model predicts a maximum reduction of ~19%, ~23% and ~30% for 1, 2 and 3 pores, respectively with a constant removal of ~12% of the atoms in all the cases. The model also predicts a higher reduction of the ballistic κl as the pore separation increases, in the case of 2, 3 and 4 pores, for the same percentage of atoms removed (~12%) in all the cases. Thus, the presence of a high number of small, well-separated pores suppress κl strongly. This reduction in ballistic κl, in the coherent limit, is attributed to the reduction of the total number of phonon modes and smaller participation of phonon modes (in κl) with increasing number of pores. (1) INTRODUCTION Silicon has been the backbone of the semiconductor industry for the last 60 years which has led to the development of very well established fabrication processes. This has resulted into numerous efforts to integrate Si as a viable thermoelectric (TE) material in solid state circuits and devices [1-4]. Bulk Si is a poor TE material (ZT ~0.06 at 300K [1]) however, Si nanowires have shown very promising room temperature thermoelectric efficiency (ZT ~0.6 at 300K) [1]. This significant improvement (~100X higher compared to bulk Si) is attributed to the drastic reduction in lattice thermal conductivity in SiNWs. Some interesting experimental [2-4] and theoretical [5, 6] efforts to further reduce the lattice thermal conductivity in silicon by creating pores in crystalline bulk Si have been reported. The artificial pore creation in crystalline Si can block the phonon transport in crystalline Si, thereby reducing the thermal conductivity as amorphours-Si (am-Si), but PC-SiNW has the advantage that the crystalline nature allows electrons to conduct quite well, thus maintaining a good electrical conductance (G) and Seebeck coefficient (S), needed for higher thermoelectric figure of merit (ZT), unlike am-Si.[5] Many technological improvements have led to the fabrication of hollow crystalline nanowires. Some of the main fabrication techniques are (i) hollow nanowire array fabrication using sacrificial templates [7], (ii) hollow spinel wires using the `Kirkendall effect' [8], (iii) electrochemical anodic dissolution [9], (iv) template based patterned nanowire fabrication [10] and (v) deep r
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