Vertical and in-plane electrical transport in InAs/InP semiconductor nanostructures
- PDF / 409,250 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 3 Downloads / 184 Views
B2.3.1
Vertical and in-plane electrical transport in InAs/InP semiconductor nanostructures K. O. Vicaro1, J. R. R. Bortoleto1,*, H. R. Gutiérrez1,**, L. Nieto1, A. A. G. von Zuben1, A. C. Seabra2, P. A. Schulz3 and M. A. Cotta1 1 Instituto de Física Gleb Wataghin, DFA/LPD, UNICAMP, CP6165, 13081-790, Campinas-SP, Brazil 2 LSI-PSI-EPUSP, USP, Av. Prof. Luciano Gualberto, trav. 3, no 158, 05508-900, São Paulo-SP, Brazil 3 Instituto de Física Gleb Wataghin, DFMC, UNICAMP, 13081-790, Campinas-SP, Brazil
ABSTRACT Vertical and in-plane electrical transport in InAs/InP semiconductors wires and dots have been investigated by conductive atomic force microscopy (C-AFM) and electrical measurements in processed devices. Localized I-V spectroscopy and spatially resolved current images (at constant bias), carried out using C-AFM in a controlled atmosphere at room temperature, show different conductances and threshold voltages for current onset on the two types of nanostructures. The processed devices were used in order to access the in-plane conductance of an assembly with a reduced number of nanostructures. On these devices, signature of two-level random telegraph noise (RTN) in the current behavior with time at constant bias is observed. These levels for electrical current can be associated to electrons removed from the wetting layer and trapped in dots and/or wires. A crossover from conduction through the continuum, associated to the wetting layer, to hopping within the nanostructures is observed with increasing temperature. This transport regime transition is confirmed by a “temperature-voltage” phase diagram.
INTRODUCTION Understanding charge transport through semiconductor nanostructures is of importance from both scientific and technological points of view. Transport measurements on nanostructured devices may be sensitive to the discrete electronic level structure. Such sensitivity may be observed for an ensemble of a low number of discrete levels participating in the transport phenomena. This situation is achieved in processed devices if only a few dozen of quantum structures effectively take part in the conduction mechanisms. In particular, transport noise measurements become an outstanding spectroscopy tool for quantum dot/wire characterization, previously applied to carrier trapping in impurities in Silicon MOS structure[1]. On the other hand, InAs/InP nanostructures provide an interesting system to study the influence of carrier localization phenomena on transport through nanostructures with different dimensionalities. InAs auto-assembles on InP in the form of nanowires and/or dots, depending on the growth conditions[2]. A transition between these two shapes is observed, and mixed structures of wires and dots can be obtained. Therefore this is a suitable candidate in order to study the electrical properties and the effect of carrier localization on nanostrutures. ____________ *
Present address: LaPTec, GPM-UNESP, Av. 3 de Março, 511, 18085-180, Sorocaba-SP, Brazil Present address: Pennsylvania State University, De
Data Loading...
