Wafer Defect Detection Using Directional Morphological Gradient Techniques
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Wafer Defect Detection Using Directional Morphological Gradient Techniques Gongyuan Qu Electrical Engineering Department, Santa Clara University, Santa Clara, CA 95053, USA Email: [email protected]
Sally L. Wood Electrical Engineering Department, Santa Clara University, Santa Clara, CA 95053, USA Email: [email protected]
Cho Teh Electrical Engineering Department, Santa Clara University, Santa Clara, CA 95053, USA Email: [email protected] Received 30 July 2001 and in revised form 12 March 2002 Accurate detection and classification of wafer defects constitute an important component of the IC production process because together they can immediately improve the yield and also provide information needed for future process improvements. One class of inspection procedures involves analyzing surface images. Because of the characteristics of the design patterns and the irregular size and shape of the defects, linear processing methods, such as Fourier transform domain filtering or Sobel edge detection, are not as well suited as morphological methods for detecting these defects. In this paper, a newly developed morphological gradient technique using directional components is applied to the detection and isolation of wafer defects. The new methods are computationally efficient and do not rely on a priori knowledge of the specific design pattern to detect particles, scratches, stains, or missing pattern areas. The directional components of the morphological gradient technique allow direction specific edge suppression and reduce the noise sensitivity. Theoretical analysis and several examples are used to demonstrate the performance of the directional morphological gradient methods. Keywords and phrases: morphological gradient, edge detection, edge orientation, wafer inspection.
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INTRODUCTION
With the increasing gate density of very large scale integration (VLSI) designs, defects in a wafer are more likely to cause failures of chip production and lower yields, which is a significant problem considering the substantial financial investment in fabrication plants. Intensive defect control procedures during integrated circuit (IC) production can help improve yields in several ways. Early detection of defects can be used to predict the yield. For wafers that have so many defects that the predicted yield would be unacceptably low, further processing can be terminated. In addition, analysis of the defects to identify the type and probable sources can be used to improve the production process. A great variety of process defects may occur over all technological steps in VLSI and application specific integrated circuit (ASIC) production. Well-known examples are oxidation stacking faults, spikes, residues from chemicals, etching defects, and different kinds of particles [1]. This paper applies detection methods
to defects that result in scratches or spots due to particles, stains, or missing pattern areas. A variety of methods and technologies have been applied to defect inspection of wafers [1, 2, 3, 4, 5, 6, 7, 8, 9]. Visual inspectio
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