Wafer map defect pattern classification based on convolutional neural network features and error-correcting output codes
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Wafer map defect pattern classification based on convolutional neural network features and error-correcting output codes Cheng Hao Jin1
· Hyun-Jin Kim2
· Yongjun Piao3
· Meijing Li4
· Minghao Piao5
Received: 9 July 2019 / Accepted: 22 January 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Defect clusters on the wafer map can provide important clue to identify the process failures so that it is important to accurately classify the defect patterns into corresponding pattern types. In this research, we present an image-based wafer map defect pattern classification method. The presented method consists of two main steps: without any specific preprocessing, highlevel features are extracted from convolutional neural network and then the extracted features are fed to combination of error-correcting output codes and support vector machines for wafer map defect pattern classification. To the best of our knowledge, no prior work has applied the presented method for wafer map defect pattern classification. Experimental results tested on 20,000 wafer maps show the superiority of presented method and the overall classification accuracy is up to 98.43%. Keywords Wafer map · Defect pattern classification · Deep learning · Convolutional neural network · Error-correcting output codes · Support vector machine · Multi-class classification
Abbreviations CNN ECOC SVM CNN-SVM OPTICS
B
Convolutional neural networks Error-correcting output codes Support vector machines SVM classification based on CNN features Ordering point to identify the cluster structure
Minghao Piao [email protected]
CART NB kNN ReLU LDA LOGISTIC CNN-ECOC-X
ANOVA SVE
Classification and regression trees Naive Bayes k-nearest neighbors Rectified linear unit Linear discriminant analysis Logistic regression Use CNN features for ECOC classification where X is used as binary classifiers Analysis of variance Soft voting ensemble
Cheng Hao Jin [email protected] Hyun-Jin Kim [email protected] Yongjun Piao [email protected] Meijing Li [email protected] 1
ENN Research Institute of Digital Technology, Beijing, China
2
BISTel, Seoul 06754, South Korea
3
School of Medicine, Nankai University, Tianjin, China
4
College of Information Engineering, Shanghai Maritime University, Shanghai, China
5
Department of Computer Science, Chungbuk National University, Cheongju 28644, South Korea
Introduction The semiconductor wafer fabrication is a complex, long and costly process which involves hundreds of complicated chemical steps and requires monitoring a great number of process parameters (Chien et al. 2014). Due to such a complexity, it is nearly impossible to produce wafers without any defects even operated by well-trained process engineers with highly automated and precisely positioned equipments in a nearly particle-free environment (Wang et al. 2006). Wafer map is a graphical representation of a silicon wafer at which all the good and defective die are contained. Wafer map defects are usually formed in clusters (Ha
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