WiFi Receiver Evolution in a Dense Blocker Environment
This paper presents three different WiFi receiver chain lineups using a high dynamic range continuous time Sigma Delta A/D converter (SD-ADC). The chains tradeoffs are analyzed from the perspective of the ADC design. The key performance indexes are perfor
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WiFi Receiver Evolution in a Dense Blocker Environment Patrick Torta, Antonio Di Giandomenico, Lukas Dörrer, and Jose Luis Ceballos
1.1 Introduction The most demanding scenario that a receiver chain must sustain is a dense blocker environment where many contiguous receiving channels are allocated and simultaneously in use by many users. In such a scenario the signal to be converted in the band of interest can be transmitted from a far station and can therefore be very weak compared to the transmitted signal of a near user. The WiFi transceiver can be embedded into a platform which serves also other standards like cellular, GNSS, BT or FM radio in a co-running mode. As the isolation of the antenna is limited to approximately 10–12 dB, it is important to ensure that other signals do not degrade the wanted signal due to alias, folding or distortion. The analysis of all possible disturber combinations is a difficult task, in particular when the A/D clock frequency is low and its multiples can generate intermodulation products and folding effects together with the receiver chain mixer clock. Figure 1.1 shows a baseband spectrum scenario and a receiver chain composed by many consecutive filter-and-gain stages followed by a medium resolution ADC. The ADC is clocked at twice of the Nyquist rate of the wanted signal bandwidth. A very high chain gain is needed to provide sufficient signal to noise and distortion ratio (SNDR) at the ADC input: this sets stringent constraints to all the baseband blocks. In particular the chain strongly amplifies the non-idealities of the blocks immediately following the mixer. The frequency behavior of the analog active components can be strongly affected by poorly controllable parasitics and even by the configuration settings for the block bandwidth and the gain. For instance, the DC offset of the mixer as well as the I-Q skew of the direct conversion receiver need to be carefully controlled and
P. Torta () • A. Di Giandomenico • L. Dörrer • J.L. Ceballos Intel Austria GmbH, Villach, Austria e-mail: [email protected] © Springer International Publishing Switzerland 2017 A. Baschirotto et al. (eds.), Wideband Continuous-time ˙ ADCs, Automotive Electronics, and Power Management, DOI 10.1007/978-3-319-41670-0_1
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Fig. 1.1 A filter and gain receiver chain and the spectrum at the ADC input
mapped to all chain configurations to guarantee high chain resolution. A low noise DC offset cancellation may be required. This leads to complex gain and calibration schemes. When an oversampled high resolution ADC is used, the chain can keep the required inband SNDR and, at the same time, absorb the power of the out of band signals employing a lower chain gain. This relaxes some analog blocks requirements and the amount of digital calibrations needed. The receiver lineups presented in Fig. 1.2 are minimal receiver architectures implementing high dynamic range (DR) continuous time sigma delta ADC (SD-ADC). The upper one implements only one active filter stage with trans-impedanc
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