Wrapper scan chain design algorithm for testing of embedded cores based on chaotic dragonfly algorithm
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RESEARCH PAPER
Wrapper scan chain design algorithm for testing of embedded cores based on chaotic dragonfly algorithm Tian Zhou1 · Cong Hu2 · Aijun Zhu2 · Chuanpei Xu2 · Chunting Wan2 Received: 27 May 2020 / Revised: 17 September 2020 / Accepted: 6 October 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract As embedded pre-designed and pre-validated cores in system-on-chip (SoC) designs have increased usage, the wrapper scan chain design (WSCD) for the embedded cores is one of the fundamental ways to reduce the SoC test time. In this paper, a chaotic dragonfly algorithm (CDA) for WSCD is proposed to minimize the test time of embedded cores by balancing the packaged scan chains (WSCs).Since the WSCD problem is non-continuous, we improve the dragonfly algorithm (DA) with integer coding to make it suitable for the WSCD problem. In order to improve population diversity and prevent falling into local optimum state, we introduce chaotic strategy into DA. Furthermore, a repaired operator that considers the specific knowledge is added to the DA. Since the CDA is a swarm intelligence method, it is expected to effectively solve the NP-hard problem. The experimental results on ITC’02 SoC benchmark show that the proposed algorithm can improve the balanced results and shorten the test time compared with the existing algorithms. Keywords SoC testing · Wrapper scan chain design · Chaotic map · Dragonfly algorithm
1 Introduction Today, advanced manufacturing of silicon chips make it possible to integrate an increased number of transistors, which permits the inclusion of hundreds of embedded cores with diverse structures on a single die, including Timer, read-only memory (ROM), digital signal processors (DSPs), combinational logic blocks (CLBs) and central processing units (CPUs), among others [1–3]. Since the reuse of pre-devised and pre-validated embedded cores significantly reduces the entire design cycle and cost, the paradigm becomes indispensable in the SoC design [4, 5]. However, with the increase in the density of embedded cores, the defects and faults in the SoC become more serious [6]. Therefore, the verification and testing of the embedded cores are significant for the successful SoC design [7]. To avoid becoming a bottleneck in SoC development, test development is also recommended as core-based.[8]. * Cong Hu [email protected] 1
School of Electronic Information and Automation, Guilin University of Aerospace Technology, Guilin 541004, China
School of Electronic Engineering and Automation, Guilin University of Electronic Technology, Guilin 541004, China
2
To this end, a conceptual test access infrastructure for embedded cores is introduced, as shown in Fig. 1.[9]. Testing consists of three structural elements: (1) test pattern source/sink (TPSo/TPSi), (2) test access mechanism (TAM) and (3) core test wrapper (CTW). The function of test pattern source is to generate test vectors for embedded cores, while the role of the test pattern sink is to analyze the responses and to provide test
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