A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications
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A 0.3-V 8.72-nW OTA with Bulk-Driven Low-Impedance Compensation for Ultra-Low Power Applications Siwan Dong1
· Yu Wang2 · Xingyuan Tong1 · Yarong Wang1 · Cong Liu1
Received: 29 August 2020 / Revised: 23 October 2020 / Accepted: 27 October 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract A bulk-driven low-impedance compensation technique is proposed for ultra-low supply voltage amplifiers. By using the low resistance node of the current mirror of input, the efficiency of Miller compensation capacitor is greatly improved. By using this compensation method, a rail-to-rail input & output bulk-driven fully differential operational amplifier is also presented in the paper. The effectiveness of the circuit has been verified in a 65 nm CMOS process, the proposed three-stage amplifier has over 70.69 dB gain, 19.95 kHz gain-bandwidth product, and 69.7° phase margin while consuming only 8.72 nW power, and occupying die area of 0.00082 mm2 from a 0.3 V supply while driving a 100pF load. Keywords Bulk-driven · Ultra-low power · Rail-to-rail · Three-stage amplifier · Miller compensation · PVT stabilization
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Siwan Dong [email protected] Yu Wang [email protected] Xingyuan Tong [email protected] Yarong Wang [email protected] Cong Liu [email protected]
1
School of Electronic Engineering, Xi’an University of Posts & Telecommunications, Xi’an 710121, China
2
Department of Electrical Engineering, Wright State University, Dayton, OH, USA
Circuits, Systems, and Signal Processing
1 Introduction The mixed-signal chips in portable electronic devices such as smart phones and smart watches, are power hungry systems, and the demand for efficient ultra-low power circuits is increasing just as rapidly due to the required battery operations of these handheld devices [1, 2]. These devices usually have an ultra-low supply voltage in order to reduce power consumption and safety [3]. The operational amplifier (OTA) is the key part of signal processing in all analog or mixed-signal low-voltage & low power systems like analog to digital converters (ADCs) [4–6]. With the lower supply voltage to meet the power consumption specification, traditional amplifier design method is becoming more and more overwhelmed such as stacking cascode transistors to improve the gain of OTA [7]. These methods are no longer suitable for ultra-low supply voltage (< 0.5 V) applications. One of the most promising approaches to design ultra-low supply voltage amplifiers is based on the application of subthreshold-biased bulk-driven (BD) amplifiers [8]. On the other hand, with the decreasing of critical dimension in integrated circuits, the intrinsic gain of the MOSFET has dropped to less than 20 s in deep submicron technology, and it will continue to decrease with further scaling [9]. The mode of vertical stacking of MOSFETs (cascode, gain-boost) must be replaced by the horizontal cascading way (three-stage, four-stage) [10]. Among them, three-stage OTA topologies become more and more popular in ultra-low supply application. It can achi
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