A Silicon on Nothing LDMOS with Two Air Pillars in Gate Insulator for Power Applications
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ORIGINAL PAPER
A Silicon on Nothing LDMOS with Two Air Pillars in Gate Insulator for Power Applications Mahsa Hanaei 1 & Ali A. Orouji 1 & Zeinab Ramezani 2 & I. S. Amiri 3,4 Received: 3 September 2019 / Accepted: 12 December 2019 # Springer Nature B.V. 2020
Abstract This paper proposes a new silicon on nothing lateral double-diffused metal-oxide-semiconductor with two air gaps in the gate insulator (SON-APG LDMOS). Utilizing air for the buried layer and placing two air pillars in gate oxide has improved DC and AC characteristics of the transistor. 2-D simulation results of ATLAS simulator illustrate a 50% enhancement in the breakdown voltage compared to a conventional SOI-LDMOS (C-LDMOS). Besides, the on-state resistance reduces 60% as a result of drain current augmentation in the SON-APG LDMOS. Moreover, the RF feature of the SON-APG LDMOS improves due to the enhancement in the gate capacitances of the transistor. Therefore, the cut-off (fT), as well as maximum oscillation frequency (fMax), grows. The extra noise that the device adds to the signal reaching the load (Noise Figure) has improved in the proposed structure. Keywords Breakdown voltage . Gate capacitance . On-state resistance . Silicon-on-nothing . Cut-off frequency . Maximum oscillation frequency
1 Introduction LDMOS transistor is a critical constituent of power electronic equipment and power amplifiers for radio frequency applications. In the design of LDMOS transistors strategies which enhance breakdown voltage, brings about deterioration of * I. S. Amiri [email protected] Mahsa Hanaei [email protected] Ali A. Orouji [email protected] Zeinab Ramezani [email protected] 1
Electrical and Computer Engineering Department, Semnan University, Semnan, Iran
2
Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA
3
Computational Optics Research Group, Advanced Institute of Materials Science, Ton Duc Thang University, Ho Chi Minh City, Vietnam
4
Faculty of Applied Sciences, Ton Duc Thang University, Ho Chi Minh City, Vietnam
the on-state resistance. The optimized LDMOS transistor is the one that strengthens breakdown voltage (BV) and decreases the on-state resistance (Ron) [1, 2]. Silicon-oninsulator (SOI) is widely utilized in the integrated power electronics owing to the strengths of SOI technology, such as reduced parasitic capacitances and substrate loss, high switching speed and perfect isolation (lower leakage) [3–5]. These features lead to improvement of parasitic capacitance and the smaller the parasitic capacitance, the faster will the transistor work [6, 7]. Due to the BOX layer, there are no unwanted leakage paths that are far from the gate. But this technology suffers from significant drawbacks such as low breakdown voltage, high on-state resistance and high gate capacitance [8, 9]. To solve the mentioned problems the SON technology is introduced. The SON structure would seem auspicious for being employed in a wide range of recent technologies, such as MEMS, waveguid
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