A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs
- PDF / 1,387,550 Bytes
- 17 Pages / 595.224 x 790.955 pts Page_size
- 3 Downloads / 247 Views
A Framework for Hardware Trojan Vulnerability Estimation and Localization in RTL Designs Sheikh Ariful Islam1 · Love Kumar Sah1 · Srinivas Katkoori1 Received: 24 September 2019 / Accepted: 7 July 2020 / Published online: 27 August 2020 © Springer Nature Switzerland AG 2020
Abstract As the design complexity increases, the attack space for malicious modifications in the design also increases. Attackers in untrusted phases during the Integrated Circuit (IC) design cycle may embed a Hardware Trojan (HT). A potential and stealthy HT is triggered with nets that rarely switch during regular circuit operation. Detection of HT in the host design requires exhaustive simulation to activate the HT during pre- and post-silicon. For analyzing HT vulnerability, we present a modeling approach to capture the rare nets using word-level statistics of the inputs. It provides the capability to locate macro-block(s) in a Register Transfer Level (RTL) design to estimate the rare triggering nets. Given RTL description of a design, we decompose the design into a subset of basic arithmetic modules, each of which is pre-characterized (empirically and analytically) by which we evaluate the design for quick estimation of HT vulnerable macro-block(s). The relative impact of mapping the design to a particular module from its analytical characteristics can be used to detect “low activity” and “local regions” without expensive low-level simulation. We implement the model over a wide range of input signal statistics for Digital Signal Processing (DSP) Intellectual Property (IP) cores, and the average estimation error for different bit-widths and correlations is less than 2%. We also propose cost functions during mapping and show that identification of rare activity blocks (nets) at a higher level is closely related to the simulation results. The final mapping that identifies the candidate arithmetic modules can minimize HT vulnerability in design at the cost of accuracy. Keywords Hardware Trojan · Word-level Modeling · Mapping · RTL arithmetic block · Localization
1 Introduction With the ever-increasing complexity of sub-nanometer transistor technologies and the prohibitive cost of fabrication, outsourcing has become a common trend in the fabless design approach. As multiple parties have become involved in IC supply chain, it lacks a centralized control of the multi-party trust. In the long electronics supply chain with untrusted entities, IC has become prone to malicious
Sheikh Ariful Islam
[email protected] Love Kumar Sah [email protected] Srinivas Katkoori [email protected] 1
Department of Computer Science and Engineering, University of South Florida, Tampa, FL, USA
modifications. Various malicious manipulations (insertions or deletions) exist that modify parts of the design so that an attacker objective is achieved. Such covert manipulations, known as Hardware Trojan (HT), may affect the system by leaking the secret information, disabling parts of the system, weakening performance with early failures. Insertion of HT into the
Data Loading...
