A Method for Finding Multiple DC Operating Points of Short Channel CMOS Circuits
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A Method for Finding Multiple DC Operating Points of Short Channel CMOS Circuits Michał Tadeusiewicz · Stanisław Hałgas
Received: 22 November 2012 / Revised: 14 March 2013 © The Author(s) 2013. This article is published with open access at Springerlink.com
Abstract This paper is devoted to the analysis of CMOS transistor circuits, fabricated in nanometer technology, having multiple DC operating points. The MOS transistors are characterised by the intricate PSP 103.1.1 model elected by the CMC as a standard. To find the operating points an approach is proposed based on a mathematical concept called a deflation. According to this concept the equations describing the circuit are deformed to avoid the solutions earlier determined and retain the remaining solutions. A new efficient deflation technique is developed and combined with the homotopy method and the discrete circuit equivalent of the Newton–Raphson nodal analysis. An algorithm has been worked out for finding multiple DC operating points of CMOS circuits encountered in practical applications. To illustrate the proposed approach three numerical examples are given. Keywords CMOS circuits · DC analysis · Deflation technique · Multiple operating points
1 Introduction Finding multiple DC operating points of nonlinear circuits is a basic question of the analysis and design and a difficult task in circuit simulation. The methods which guarantee finding all the DC operating points are very time consuming, capable of analysing only small size circuits. They employ different mathematical concepts and computation techniques, e.g. linear programming [14], interval analysis [11], the idea M. Tadeusiewicz () · S. Hałgas Department of Electrical, Electronic, Computer and Control Engineering, Technical University of Łód´z, ul. Stefanowskiego 18/22, 90-924 Łód´z, Poland e-mail: [email protected] S. Hałgas e-mail: [email protected]
Circuits Syst Signal Process
of successive contraction, division and elimination of some hyperrectangular regions where the solutions are sought [17, 18, 20], the theory of monotonic operators [19], and the simplex method [25]. Recently several methods have been published which are capable of finding multiple DC operating points but do not guarantee finding all of them [5, 7, 10, 13, 15, 21–24]. They are less time consuming and do not require a high computing power. Consequently, more complex circuits can be analysed. In reference [21] the deflation concept is used to analyse circuits containing diodes and bipolar transistors having multiple DC operating points. In this paper the deflation technique is extended to CMOS circuits manufactured in nanometer technology. CMOS electronic circuits fabricated in nanometer technology contain transistors characterised by very complicated DC models, PSP or BSIM 4. Each of the models is described by several hundred nonlinear equations. Consequently, the analysis of these circuits, even when there is a unique solution, is very time consuming and uncertain. This is why the programs based
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