A Model for Dopant Pile-Up at the Interface in a Self-Aligned Polysilicon-Emitter Process
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A MODEL FOR DOPANT PILE-UP AT THE INTERFACE IN A SELF-ALIGNED POLYSILICON-EMITTER PROCESS DOROTHEA E. BURK AND SHUY-YOUNG YUNG Dept. of Electrical Engineering, University Florida 32611.
of
Florida,
Gainesville,
ABSTRACT A model for dopant pile-up in conjunction with a self-aligned polysilicon-emitter process model is presented that accurately predicts the total dopant profiles of the polysilicon layer, the interfacial pile-up and The pile-up model the underlying emitter, taken from SIMS measurements. assumes that, after the dopant is implanted into the polysilicon layer and instantaneously redistributes there during the anneal, the dopant diffuses from its polysilicon source into the interfacial and underlying base region. In the disordered interfacial region, the dopant transport occurs by hopping, with a, certain fraction of dopant sticking in vacant sites. As further The model for dopant pile-up is implemented into SUPREM III. using the respective electrically active support, device simulations, dopant profiles, are found to be in good agreement with measurements on self-aligned phosphorus-implanted transistors. INTRODUCTION Dopant pile-up at the interface between the polysilicon layer and the underlying emitter in a self-aligned polysilicon-emitter process can affect the
electrical
properties
and
the
impurity
distribution
during
emitter
The major formation of the high-performance bipolar transistor [1-3] effects of dopant pile-up on the electrical properties of the emitter have already been modeled [4], but there have been very few attempts to model Because the mechanism for or the amount of pile-up at the interface [1]. the total number of dopants piled up at the interface can be as much as one half of the total number of dopants in the underlying emitter, modeling the pile-up can result in more accurate simulation of the underlying-emitter total and active dopant profile, which is important in predicting the device behavior. In the self-aligned process, the bipolar transistor is fabricated up After the emitter window is opened, a polysilicon through the base. During the contact is deposited, implanted with dopant, and annealed. activation anneal, the polysilicon recrystallizes and the dopant diffuses into the base region underlying the contact, thus forming a self-aligned polysilicon-contacted emitter. In Fig. 1, typical SIMS and spreading resistance profiles are given for two self-aligned emitter processes [5]. [The SIMS profiles give the total dopant concentration, while the spreading active dopant resistance measurements give the net electrically concentration. Consequently, the spreading resistance profiles in Fig. 1 are for the n-type, phosphorus emitter (* .* ) and p-type base region (AA A A) and cannot be directly compared with the SIMS profiles.] From a comparison of the two profiles, the piled-up dopant at the interface between the polysilicon contact and underlying emitter is in high concentrations and not all electrically active. It is the effect of this dopant pile-up at interface on
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