2D Dopant Profiling for Advanced Process Control
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2D Dopant Profiling for Advanced Process Control Xiang-Dong Wang, Qianghua Xie, Joe Hooker, Shifeng Lu, JJ Lee, Phil Tobin Advanced Products Research and Development Labs (APRDL), Motorola Inc, 2100 E. Elliot Rd. Maildrop EL622, Tempe, AZ 85284 Wei Liu, MOS12, Motorola Inc, Chandler, AZ. Linda Cross, MOS11, Motorola Inc, Austin, TX ABSTRACT As the CMOS device dimensions continue to shrink, it is more and more critical to control the process parameters during mass production of advanced VLSI chips in order to achieve high yield and profitability. 2D dopant characterization is one of the critical techniques to resolve manufacturing excursions. A quick access to dopant distribution, especially precise delineation of p-n junction would readily provide critical information for many manufacturing issues, as well as device design and process development. Here we present our approaches to some of those issues with available techniques. The main techniques we used are dopant selective etching (DSE) and scanning probe microscopy based electrical measurements including scanning capacitance microscopy (SCM) and scanning spread resistance microscopy (SSRM). These techniques provided complementary results and showed strengths in solving different issues. We have successfully delineated junction of CMOS devices with 0.13 µm technology with source/drain extensions. Other applications, including diode leakage, well-well isolation, and buried layer delineation with the combination of these methods are presented.
INTRODUCTION As the advance of VLSI technologies, the control of semiconductor chip fabrication processes is becoming more stringent and process issues need be addressed in a timely manner. Efficient 2D dopant characterization is a critical measure to ensure device functionality, however this is an area that a lot of new challenges need to be addressed. In the past few years, a great deal of effort has been devoted to the development of a complete solution for 2D dopant profiling with capabilities outlined in The International Roadmap for Semiconductor Technology (IRST)[1]. Significant progress has been made by using scanning probe microscopy based techniques [2-5], TEM electron holography[6], dopant selective etching (DSE)[7-9], and recently atom probe field ion microscope (AP-FIM) [10]. However, these techniques are not mature enough to solve practical manufacturing issues that demand fast turn around time. In this paper we report the improvement and utilization of existing techniques for issues related to 2D dopant characterization. The main techniques we used are dopant selective etching (DSE) and scanning probe microscopy based electrical measurements including scanning capacitance microscopy (SCM) and scanning spread resistance microscopy (SSRM). These techniques are complementary to each other and exhibited strengths in solving different issues. Examples are presented in the paper by using mainly DSE and SCM techniques.
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RESULTS AND DISCUSSION DSE or junction staining is widely used in semiconductor i
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