A physically-based SPICE model for the leakage current in a-Si:H TFTs accounting for its dependencies on process, geomet
- PDF / 211,547 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 59 Downloads / 191 Views
A physically-based SPICE model for the leakage current in a-Si:H TFTs accounting for its dependencies on process, geometrical, and bias conditions Peyman Servati, Arokia Nathan and Andrei Sazonov Department of Electrical & Computer Engineering, University of Waterloo, Waterloo, Ontario, Canada N2L 3G1 ABSTRACT We have developed a physically-based analytical model of the static current-voltage characteristics of hydrogenated amorphous silicon (a-Si:H) inverted staggered thin film transistors (TFTs) in the reverse (leakage) regime (VG0). We studied analytically (based on measurement data) the dependence of the leakage current on process parameters (i.e. the deposition-temperature-dependent phosphorus diffusion profile in the a-Si:H active layer), geometrical parameters (i.e. a-Si:H thickness, source/drain overlap areas), and operating conditions (i.e. VG, VD). The derived analytical model is implemented in HSPICE. The simulated and measured results are in good agreement with a discrepancy of less than 5%. INTRODUCTION The a-Si:H TFT is widely used for active matrix liquid crystal displays (AMLCD) and imaging applications. In imaging arrays, the TFT is used as a switching element that connects each pixel to readout circuitry. In its OFF-state, the TFT should drain very little or no charge from the sensor so as to not significantly undermine the signal-to-noise ratio. Therefore, a study of the leakage current for its subsequent reduction is critical. This constitutes the focus of this article. There are three distinguishable mechanisms that can be identified to be the source of leakage current in a-Si:H TFTs. Depending on the bias regime, one or the other mechanism prevails to determine the characteristics of the TFT in that regime. OHMIC CONDUCTION THROUGH NITRIDE GATE INSULATOR The ohmic conduction through the a-Si:H and a-SiNx:H layers prevails at low gate voltages (-5
Data Loading...
