A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis
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Research Article A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis Rasmus Abildgren,1 Jean-Philippe Diguet,2 Pierre Bomel,2 Guy Gogniat,2 Peter Koch,3 and Yannick Le Moullec3 1 CISS,
Aalborg University, Selma Lagerl¨ofs Vej 300, 9220 Aalborg East, Denmark (UMR CNRS 3192), Universit´e de Bretagne Sud, Centre de recherche, BP 92116, 56321 Lorient Cedex, France 3 CSDR, Aalborg University, Fredriks Bajers Vej 7, 9220 Aalborg East, Denmark 2 Lab-STICC
Correspondence should be addressed to Rasmus Abildgren, [email protected] Received 15 March 2008; Revised 30 June 2008; Accepted 18 September 2008 Recommended by Markus Rupp This paper presents a metric-based approach for estimating the hardware implementation effort (in terms of time) for an application in relation to the number of linear-independent paths of its algorithms. We exploit the relation between the number of edges and linear-independent paths in an algorithm and the corresponding implementation effort. We propose an adaptation of the concept of cyclomatic complexity, complemented with a correction function to take designers’ learning curve and experience into account. Our experimental results, composed of a training and a validation phase, show that with the proposed approach it is possible to estimate the hardware implementation effort. This approach, part of our light design space exploration concept, is implemented in our framework “Design-Trotter” and offers a new type of tool that can help designers and managers to reduce the time-to-market factor by better estimating the required implementation effort. Copyright © 2008 Rasmus Abildgren et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
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INTRODUCTION
1.1. Discussion of the problem Companies developing embedded systems based on highend technology in areas such as telecommunication, defence, consumer products, healthcare equipment are evolving in an extremely competitive globalised market. In order to preserve their competitiveness, they have to deal with several contradicting objectives: on one hand, they have to face the ever-increasing need for shorter time-to-market; and on the other hand, they have to develop and produce low-cost, highquality, and innovative products. This raises major challenges for most companies, especially for small- and medium-sized enterprises (SMEs). Although SMEs are under pressure due to the abovementioned factors, they are either not applying the latest design methodologies or cannot afford the modern electronic system level (ESL) design tools. By limiting themselves to traditional design methodologies, SMEs make themselves more vulnerable to unforeseen problems in the development
process, making the time-to-market factor one of the most critical challenges they have to deal with. A survey released at the Embedded Systems Conference (ESC 2006) [1] indicated that m
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