A reusable stage based reduced comparator count binary search ADC
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A reusable stage based reduced comparator count binary search ADC Dipti1 • Sajai Vir Singh2 • Rohit Joshi1 • Prasanna Kumar Misra1 • Manish Goswami1 Received: 23 December 2019 / Revised: 28 April 2020 / Accepted: 29 June 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract A 4- bit reusable stage based asynchronous binary search analog to digital converter (ADC) with a smart switching network, and reduced comparator count is presented in this paper. The proposed ADC uses asynchronous logic to activate comparators sequentially while switching network is used to provide reference voltages for selected comparators. In the extended version, the 6-bit ADC is designed using only ðN þ 1Þ comparators instead of 2ðNÞ 1 and (2N - 1) as used in conventional approach. The simulation results of 4 bit ADC confirms that the design achieves conversion speed of 500 MSPS with power consumption of 1.63 mW when operated on 1.8 V supply with SNR, SFDR and ENOB as 22.5 dB, 32.4 dBc and 3.8 bits while for 6 bit the SNR, SFDR and ENOB are 34.96 dB, 42 dBc and 5.56 bits respectively with 0.35 mW of power dissipation. The Walden FOM for proposed 4 bit and 6 bit ADC design are 0.21 pJ/conversion-step and 24.7 fJ/conversion-step respectively. Keywords Analog to digital converter (ADC) Successive approximation register (SAR) Low power design Binary search ADC
1 Introduction ADC is used to convert analog signals into digital domain [1] for many fields of applications including software radios, smart antennas, digital satellite payloads, radars and medical imaging etc [2, 3]. For these applications, ADCs must dissipate low power to increase the lifetime of battery based portable devices [4]. Generally for design targeting high speed and low chip area architecture, flash ADC and SAR ADC are respectively preferred. Due to low latency and less conversion time, the flash ADC is often preferred for applications of high speed [5–7] but in flash ADC, the comparator count is 2ðNÞ 1, where N is resolution. Therefore, the hardware complexity increases with resolution and eventually power consumption increases due to activation of all comparators at the same time. On the other
& Manish Goswami [email protected] 1
Electronics and Communication Engineering, Microelectronics Division, Indian Institute of Information Technology Allahabad, Prayagraj, Uttar Pradesh, India
2
Department of Electronics and Communication Engineering, Jaypee Institute of Information Technology, Noida, India
hand, SAR ADC has less area and lower power consumption as it consists of single comparator in its architecture. However, due to many comparisons, it takes more settling time which limits its conversion speed [8]. Therefore, the need of balanced architecture between flash and SAR ADC was always desired and had been eventually fulfilled by the birth of binary search ADCs [9–11]. Figure 1 represents the structure of binary search ADC which has 2ðNÞ 1 comparator counts similar to flash ADC but it activates each comparator seque
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