Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current
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Low power 9-bit 500 kS/s 2-stage cyclic ADC using OTA variable bias current Jose´ A´ngel Dı´az-Madrid1 • Gine´s Dome´nech-Asensi2 Jose´ Javier Martı´nez2
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Ramo´n Ruiz-Merino2 • Juan Zapata2
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Received: 11 February 2020 / Revised: 22 June 2020 / Accepted: 26 July 2020 Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents a 9-bit, 2-stage cyclic analog to digital converter (ADC) with a variable bias current control circuitry to reduce its power dissipation. Each stage outputs a three-bit digital word and the circuit requires four subcycles to perform a whole conversion. Since the accuracy required is higher in the first stage and first subcycle and decreases in subsequent cycles, the bias current of each operational transconductance amplifier is regulated depending on the subcycle of the conversion process. The resolution and sampling frequency of the converter make it suitable to be integrated with 8-bit CMOS imagers with column-parallel ADC architectures. The ADC has been designed using a 1.2 V 110 nm CMOS technology and the circuit consumes 27.9 lW at a sampling rate of 500 kS/s. At this sampling rate and at a 32 kHz input frequency, the circuit achieves 56 dB of SNDR and 9 bit ENOB. The Figure of Merit is 109 fJ/step. Keywords Analog-to-digital converter (ADC) CMOS OTA low power adaptive bias current
1 Introduction Analog to digital converters are circuits required in most CMOS image sensors built nowadays. These circuits usually require low power ADCs, with a resolution above 8 effective bits, very little noise and a frame rate above 30 frames per second or faster. Typical ADCs topologies employed in CMOS imagers are successive approximation (SAR) and cyclic converters [1]. Most CMOS imagers use column parallel ADC architectures, which implies that there are as many ADCs as columns in the imager, and each ADC must convert the values of the pixels of the whole column. This leads to two types of design considerations. On the one hand, the design of ADC architectures
& Gine´s Dome´nech-Asensi [email protected] 1
Departamento de Ingenierı´a y Te´cnicas Aplicadas, Centro Universitario de la Defensa CUD- UPCT, C/Coronel Lo´pez Pen˜a s/n, Base Ae´rea de San Javier, Santiago de la Ribera, 30729 Murcia, Spain
2
Dpto. de Electro´nica y Tecnologı´a de Computadoras, Universidad Polite´cnica de Cartagena, c/ Dr. Fleming s/n, 30202 Cartagena, Spain
with moderate speeds and medium resolution. In the case of CMOS image sensors using 256 Gy level, at least 9-bit resolution ADCs are needed, usually having a measured effective number of bits (ENOB) of between 8 and 9 bits. On the other hand, each converter must fit within the width of an imager column, which implies some area restrictions. Although SAR converters are simple and efficient, they tend to occupy a larger area since its DAC requires 2n capacitors, being n the resolution of the converter, compared to only two capacitors per stage required by a cyclic circuit [2]. Moreover, their performance can be limi
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