A Simple Technique for Sub-10 nm Planar Nanofluidic Channel Fabrication
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1222-DD05-08
A Simple Technique for Sub-10 nm Planar Nanofluidic Channel Fabrication Chunrong Song and Pingshan Wang Department of Electrical and Computer Engineering, Clemson University, Clemson, SC 29634, U.S.A. ABSTRACT A simple and low-cost technique is demonstrated to fabricate sub-10 nm planar nanofluidic channels. Native oxide on silicon surface is etched with a multiple hydrofluoric (HF)-etch / SiO2regrowth process. Shallow Si trenches with 3 nm to 24 nm depths are obtained at an etch rate of 1 nm per HF dip. The trenches are uniform with a surface r.m.s. roughness of 0.4 - 0.6 nm. A low-temperature and low-voltage anodic wafer bonding process is then used to form planar nanofluidic channels. Minimum aspect ratio (depth/width) of the fabricated sub-10 nm nanochannels is around 0.001-0.002. INTRODUCTION Nanochannels have attracted great attention in recent years because new material properties and new applications emerge when their critical dimensions approach one nanometer. Typical applications include DNA analysis [1], protein detection [2], single molecule studies [3], electrokinetic energy conversion efficiency [4], nanofludic transistors [5] and diodes [6]. Therefore, fabricating such nanochannel in a controllable fashion is one of the critical issues in nanofluidics, nanobiotechnology, and fluidic electronic development. As a result, many efforts have been devoted to developing a reliable and reproducible fabrication strategy to build sub-10 nm nanofluidic channels, such as a 9-nm wide self-enclosed, self-limited silicon-dioxide (SiO2) nanofluidic channel through nanolithography [7], a 7 nm slit-like non-planar nanofluidic channel through a nanoglassblowing method [8], a 10 nm enclosed nanofluidic channel through nanoimprint lithography [9], a 10 nm channel through polysisesquioxane sealing [10], and 5-6 nm planar nanofluidic channels through thermal oxide growth and wafer fusion bonding [11]. Among these nanofluidic channels, shallow planar ones are attractive because expensive nanolithography processes are avoided [12]. Bulk nanomachining and wafer bonding are commonly used techniques to fabricate planar nanochannels. Shallow trenches are etched into a wafer (bottom wafer) via dry etch or wet etch first. Then a second wafer (top wafer) is bonded to the bottom one through wafer bonding to seal the trenches and form the nanochannels. The critical dimension of the obtained nanochannels is the channel depth, which is usually the same as the trench depth [12]. As a result, sub-10 nm trench etch and wafer bonding are two key process steps for sub-10 nm planar nanochannels fabrications. Tetramethylammonium hydroxide (TMAH) silicon etch and dilute hydrofluoric (HF) SiO2 etch are two main approaches studied for shallow trench formation so far. Due to start-up problems [11], TMAH etch is usually used for Si trenches that are 20 nm or deeper. On the other hand, SiO2 trench depth is mainly determined by the space layer (oxide) thickness or HF etch time. The 5-6 nm thermal oxide trenches [11] are the shallowest r
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