100-nm Channel Length a-Si:H Vertical Thin Film Transistors
- PDF / 4,875,834 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 107 Downloads / 224 Views
I2.4.1/A3.4.1
100-nm Channel Length a-Si:H Vertical Thin Film Transistors Isaac Chan and Arokia Nathan Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, Ontario, N2L 3G1, Canada ABSTRACT This paper reports on hydrogenated amorphous silicon (a-Si:H) vertical thin film transistors (VTFTs) with channel length of 100 nm, using conventional planar TFT processing technology. The device has a fully self-aligned vertical channel structure, which is highly insensitive to the non-uniformity of reactive ion etching (RIE). Therefore, the VTFT process is very suitable for large-area electronics. Presently, we can demonstrate VTFTs with remarkable ON/OFF current ratio of more than 108, low leakage current down to 1 fA, and good subthreshold slope of 0.8 V/dec at Vd = 1.5 V. The impacts of contemporary device issues, such as short-channel effects and contact resistance, on the performance of short-channel VTFTs and suggested avenues for improvement are discussed. INTRODUCTION A vertical thin film transistor (VTFT) structure is highly promising for the fabrication of short-channel TFTs to improve the switching speed, without a strong demand on lithographic resolution [1]. The channel length of a vertical transistor is defined by the dielectric film thickness, which can be precisely controlled through the deposition time. In terms of processing technology, the thickness of plasma enhanced chemical vapor deposited (PECVD) hydrogenated amorphous silicon nitride (a-SiNx:H) can be easily controlled down to 100 nm or less. VTFT is therefore an enabling structure for sub-100 nm channel length TFTs without the need for nanolithography [2]. VTFT provides an elegant means to minimize the device size on the substrate for high packing density. These are the major attractive features that motivate the research and development of a VTFT process that is applicable to large-area flat-panel electronics [3]. IDEAL VERTICAL STRUCTURE Schematically, the channel length of a VTFT is defined by the insulating film thickness, which is orthogonal to the plane of substrate (Figure 1a). The drain / insulator / source multilayered structure serves as a vertical “substrate” where the undoped semiconductor channel, gate dielectric, and gate electrode can be deposited upon each other to form the vertical channel of the transistor. Making a transistor in this schematic structure implies that all materials in the multilayered structure should be fully self-aligned to the extent that there is no significant shadowing effect due to an undercut profile to obstruct sputter deposition of the gate metal onto its sidewall. Otherwise, the gate metal may not have sufficient coverage for the channel, leading to poor electrical performance [3].
I2.4.2/A3.4.2
(a)
M M Drain n+
Insulator
M r e to at la :H G su Si In i aL
Insulator
Gate M Insulator i a-Si:H
L
(b)
M M Drain n+
θ
nn+ + Source M Glass
n+ Source M Glass
Figure 1. Schematics of a) an ideal VTFT structure and b) a slanted VTFT structure. To circumvent this issue, some
Data Loading...
