A Study on Selective Etching of SiGe Layers in SiGe/Si Systems for Device Applications
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U11.8.1
A Study on Selective Etching of SiGe Layers in SiGe/Si Systems for Device Applications Takashi Yamazaki, Tomohide Sekikawa, Shinya Morita, Yoshitaka Hakamada, Hiroyuki Ohri, Shun-ichiro Ohmi, and Tetsushi Sakai Department of Information Processing, Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, Kanagawa 226-8502, Japan ABSTRACT Selective etching of a SiGe layer for Si/SiGe/Si stacked layers was investigated for device applications. The SiGe layer is selectively and laterally etched by a HF:HNO3:H2O solution after patterning the layers. The selective etching rate of the SiGe layer increased as the Ge ratio increased. The etching rate of a SiGe layer annealed at 800oC did not change from an as-grown sample, and the Ge diffusion into Si was very small. However, the etching rate of a layer annealed at 1000oC was found to have decreased, and Ge diffused into Si in large amounts. This indicates that annealing at less than 800oC is suitable for device applications. INTRODUCTION
CMOS downsizing has been accelerating and approaching to the sub-10 nm gate length region. One of the most critical issues in this region is current drivability. To overcome this difficulty, several three dimensional gate structures have been reported, such as Double-gate transistor [1], Vertical (Double-gate) transistor [2], and Fin FET [3]. One of these devices is a multi-layer channel MOSFET (ML-MOSFET) proposed by Sakai et al [4]. As shown in figure 1, the ML-MOSFET has a multi Si channel layer that is stacked vertically so that the drain current per 1 µm gate width on the wafer should increase as the number of channel layers increase. Based on a device simulation, an excellent drain current such as Ion = 3.9 mA/µm for an ML-MOSFET with a 3 Si channel layer (Lg: 10 nm, Tsi: 2.5 nm) was obtained. The most important process in fabricating the ML-MOSFET is forming the multi Si channel layers. Selective etching for the Si/SiGe/Si stacked layers has been proposed and developed for the process. In this technique, the SiGe layers are selectively and laterally etched after channel patterning by a HF:HNO3:H2O solution. This method is very attractive for various device applications. In this paper, the effect of the Ge contents and furnace annealing process on the selective etching was investigated in detail. Schematic cross section (at dotted line)
Electrode L g
Gate electrode Si channel
TSi Drain
Source SiO2 Si substrate
Gate oxide Spacer
(a)
SiO2 Si substrate (b)
Figure 1. Schematics of ML-MOSFET. (a) Cross-section from source to drain (3 layers in this case), and (b) cross-section at dotted line in figure 1(a).
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EXPERIMENTAL DETAILS SiGe and Cap-Si layers were grown on a chemically cleaned HF-last p-Si(100) substrate using an ultraclean hot-wall low-pressure CVD (LP-CVD) system at 500 and 550oC, respectively [5]. As source gases, 100% SiH4 and 5.3% GeH4/H2 were used for the SiGe layer, and 100% SiH4/Ar was used for the Si layer. The pressure du
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