Selective Si/SiGe Heterostructures for Advanced CMOS and BiCMOS Technologies
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grown at low temperature, which is compatible with device needs, i.e. in the order of 100 nm in thickness and below about 30% of Ge content [2]. For CMOS structures the existing designs reducing the gate length, thus decreasing the channel resistance and carrier transit time, have led to the socalled « short channel effects > [3]. To improve CMOS performances new channel parameters may be introduced such as Si or SiGe thin epitaxial layers to increase the carrier mobility by decreasing the channel doping level or carrier scattering at the Si/Si02 interface respectively [4]. In fact heterojunction band offset allows carrier confinement beneath the interface and the conduction is carried out within a buried channel [5]. Another way of improving channel conduction is by the addition of a retrograde implanted profile followed by an intrinsic selective epitaxial Si layer leading to a much lower surface doping level, thus obtaining higher mobility, lower junction capacitance and a better subthreshold slope [6]. A very important application of epitaxial SiGe is in the base of the heterojunction bipolar transistor (HBT). The reduced band gap of SiGe induces a low barrier height to electron injection into the base from the emitter, increasing the transistor gain. Moreover, the gradual composition of the SiGe layer creates a built-in drift field accelerating up the minority carriers and compensates for any mobility decrease resulting from the higly doped base region [2,8]. These heterostructures have been introduced into existing CMOS and BiCMOS technologies with well improved results compared with those obtained using standard processes. To allow that, a selective epitaxial Si and SiGe technique has been developed with special care in selectivity, layer quality and minimum device size and fillng ratio dependance. Results will be presented in growth kinetics as a function of gas mixture composition, temperature and aspect ratios in order to integrate the new structures into existing 200 mm technologies with minimum process changes. The performances of these devices will be shown and compared to those of standard structures. EXPERIMENTAL All the experiments were carried out in an industrial cluster reactor working at reduced pressure and temperature. The 200 mm wafers from the load lock are transferred into the reaction chamber. The wafer sits on a rotating SiC coated graphite susceptor and is heated from the top and bottom by two sets of power lamps through clear quartz domes. The process temperature is monitored and controled by two pyrometers, one facing the top surface of the wafer, the other the back surface of the susceptor. This configuration enables a feedback for temperature control from one or other according to the type of deposition or Si surface coating. The temperature range is between 600 to 1200'C and an in situ chamber cleaning, consisting of a high temperature cycle under HC1/H 2 gases, allows the etching off of any deposits on the transparent quartz domes. Following this, several hundred wafers are process
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