A switchable DC offset cancellation circuit for time-based degradation correction
- PDF / 1,705,293 Bytes
- 7 Pages / 595.276 x 790.866 pts Page_size
- 101 Downloads / 175 Views
A switchable DC offset cancellation circuit for time-based degradation correction Didem Erol1 • Ali Dog˘us¸ Gu¨ngo¨rdu¨1 • Gu¨nhan Du¨ndar2 • Mustafa Berke Yelten1 Received: 21 March 2020 / Revised: 21 March 2020 / Accepted: 6 September 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper focuses on observing the aging impact of a DC offset cancellation circuit (DCOC) on the performance of an amplifier subject to time-based degradation, also known as aging. The circuit can be activated or deactivated to reduce the offset voltage that arises due to possible mismatches between the aging transistor in an amplifier. The proposed DCOC is designed along with a fully differential amplifier. It is fabricated in the low power TSMC 40 nm CMOS technology by using a single power supply of 1.1 V. Post-layout simulation results demonstrate that the offset suppression can be realized both in the Monte Carlo (MC) and corner analysis. In the measurement results of the fabricated chips, the DC offset, which is present before the deactivation of the DCOC, is suppressed by 19.25 dB. Keywords DC offset cancellation RF amplifiers Common mode feedback Fully differential amplifiers Transistor aging Hot carrier injection Negative bias temperature instability Time-dependent dielectric breakdown Transistor reliability
1 Introduction High offset voltages cause significant problems for analog integrated circuits. As the device processing technology develops, the mismatch of the devices is the main reason for offset generation [1]. While shrinking device sizes reduces the power consumption and the chip area in analog and mixed-signal circuits [2, 3], they also lead to limitations due to larger transistor mismatches. Similarly, in radio frequency circuit design, the performance of receivers is decreased by the offset errors as open-loop amplifiers, which are susceptible to mismatch-based deviations, are frequently used in such systems. DC offsets caused by transistor mismatches have the potential to saturate the next stages in a multistage amplifier, thereby leading to severe system limitations [4]. Hence, it is required to employ an offset cancellation circuit to improve the accuracy and & Mustafa Berke Yelten [email protected] 1
Electronics and Communication Engineering, Istanbul Technical University, Istanbul, Turkey
2
Electrical and Electronics Engineering, Bog˘azic¸i University, Istanbul, Turkey
performance of the mixed-signal and radio-frequency systems [5]. There are several circuit design approaches to eliminate the DC offset, specifically by implementing a DC offset cancellation circuit (DCOC) through trimming, auto-zeroing, correlated double sampling, and chopper stabilization methods [6]. Trimming techniques can be categorized into subgroups of AC coupling through a high-pass filter in the feed-forward path, low-pass filtering in the feedback path, and feed-forward offset cancellation [4, 7]. In the AC coupling method, large capacitance and resistances lead to signal loss
Data Loading...
