Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor
- PDF / 1,188,332 Bytes
- 20 Pages / 595.28 x 793.7 pts Page_size
- 31 Downloads / 175 Views
RESEARCH
Open Access
Acceleration of block-matching algorithms using a custom instruction-based paradigm on a Nios II microprocessor Diego González*, Guillermo Botella, Carlos García, Manuel Prieto and Francisco Tirado
Abstract This contribution focuses on the optimization of matching-based motion estimation algorithms widely used for video coding standards using an Altera custom instruction-based paradigm and a combination of synchronous dynamic random access memory (SDRAM) with on-chip memory in Nios II processors. A complete profile of the algorithms is achieved before the optimization, which locates code leaks, and afterward, creates a custom instruction set, which is then added to the specific design, enhancing the original system. As well, every possible memory combination between on-chip memory and SDRAM has been tested to achieve the best performance. The final throughput of the complete designs are shown. This manuscript outlines a low-cost system, mapped using very large scale integration technology, which accelerates software algorithms by converting them into custom hardware logic blocks and showing the best combination between on-chip memory and SDRAM for the Nios II processor. Keyword: Computer vision, Optical flow, MPEG compression, Block-matching algorithm, Nios II, FPGA, Custom instructions, Embedded systems
1. Introduction Real-time motion estimation is an important task to be computed using machine vision technology and a multimedia scope. For example, one of the most timeconsuming issues when computing standards with video coding and transmission has to do with the ubiquitous portable consumer electronic devices, all with multimedia capabilities, that require the efficient implementation of video coding algorithms, creating a trade-off between accuracy, efficiency, and power consumption. There is a profusion of motion estimation algorithms and systems; many of them are frequently used in multimedia tasks and video coding standards, such as motion compensation and coding [1,2]. When considering motion estimation for multimedia purposes, the main point is to avoid the use of temporal redundancy of video data for storage and transmission [2,3]. Motion estimation for multimedia coding is achieved mostly through block-matching techniques * Correspondence: [email protected] Department of Computer Architecture and Automation, Complutense University, Ciudad Universitaria s/nMadrid 28040, Spain
[4-8] that analyze the macro blocks (blocks of pixels, commonly called MBs) of the reference frame in order to estimate the closest block to the one in the current frame. Accordingly, the motion vector is defined as an offset from the current frame of MB coordinates to the MB coordinates in the reference frame. An overview of the process is shown in Figure 1. This method of coding the processed frame with motion estimation using video is also known as inter-frame. There are several previous works regarding motion estimation hardware acceleration [9-11] and, specifically, block-matching algorithms [12], tho
Data Loading...
