Advances in Characterization of CMP Consumables
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Advances in
Characterization of CMP Consumables Mansour Moinpour, Alex Tregub, Andrea Oehler, and Ken Cadien
Abstract Chemical–mechanical polishing, or planarization (CMP), has emerged as an increasingly important technology for integrated-circuit manufacturing. Consumables used during CMP interact in a complex manner with the polishing tool, the process conditions, and the wafer being polished. In this article, several advanced analytical methods are used to analyze the properties of slurries and pads under conditions similar to those found during CMP processing. Some of the key findings are that under these process conditions, pads can be stabilized with a heat treatment prior to installation on the polisher; pads absorb slurries at different rates, and slurries also react with the pads; and the mechanical properties of the pads are dependent on the orientation of the grooves on the pad. Dynamic rheometry was used to detect de-agglomeration in sheared slurries. Keywords: chemical–mechanical planarization, chemical–mechanical polishing, CMP, consumables, integrated-circuit (IC) fabrication, polymer characterization, rheology.
Introduction Chemical–mechanical polishing, or planarization (CMP), has emerged as the premier technique for achieving both local and global planarization in silicon integrated-circuit (IC) manufacturing. The recent advent of CMP as a major process technology has had a significant impact on the semiconductor industry. With the transition of the Si IC fabrication industry to sub-0.5-m devices in the late 1990s, the CMP market size has grown rapidly, from $300–400 million in 1997 to over $1 billion in 2000.1 Oxide CMP has been the planarization technology used for logic and dynamic random-access memory (DRAM) devices with feature sizes of 0.8 m.2 CMP also provides a technological advantage in front-end processes such as shallow trench isolation (STI)3 and polysilicon polishing,4 as well as back-endof-the-line (BEOL) processing, where the ability of CMP to planarize, achieve high selectivity, and leave smooth surfaces provides a significant advantage over competing technologies. For logic devices with feature sizes of 0.35 m, the BEOL process consists of 5–6 layers of interlayer
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dielectric (ILD) and tungsten CMP steps.5–8 BEOL processing replaced W plasma etchback processes that resulted in large plug recesses (localized areas of W film loss) and were susceptible to incoming W deposition defects. Tungsten CMP results in sub100-nm plug recesses and actually removes incoming W deposition defects. Recently, IC fabrication technology has converted to copper dual damascene methods for BEOL processing in sub-0.18-m technology nodes. ILD and W polishing have been replaced with Cu CMP.9–11 The importance of the CMP process for BEOL processing is often described in terms of enabling the use of multiple, vertically stacked layers of metal, thus allowing the die to be as small as possible. CMP works to prevent topography from one layer propagating to the next layer. The lack of topography e
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