CMP Modeling and Characterization for Polysilicon MEMS Structures
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CMP Modeling and Characterization for Polysilicon MEMS Structures Brian Tang and Duane Boning Microsystems Technology Laboratories, MIT 60 Vassar St., Bldg. 39-328, Cambridge, MA 02139 ABSTRACT The current bedrock technology for integrated circuit (IC) planarization, chemical-mechanical polishing is beginning to play an important role in microelectromechnical systems (MEMS). However, MEMS devices operate with bigger feature sizes in comparison to ICs, in order to fulfill mechanical functions. We present an experiment to characterize and model a polysilicon CMP process with the specific goal of examining MEMS-sized test structures. We utilize previously discussed CMP models and examine whether assumptions from IC CMP can be applied to MEMS CMP. An analysis of the data collected points to a polishing dependence on not only pattern density, but also partly on feature size or feature configuration. The existing pattern density and step height CMP models are able to capture the major trends in up and down area polishing. However, certain layout features relevant to MEMS are difficult to predict, motivating the need for further model development and application. INTRODUCTION Chemical-Mechanical Polishing (CMP) serves as the dominant method for wafer planarization in the integrated circuit industry. However, most past work examining CMP has focused on the ever-shrinking feature sizes in integrated circuits. The microelectromechanical systems (MEMS) industry, on the other hand, does not necessarily gain the same benefits from miniaturization. Mechanical structures might require features orders of magnitude larger than transistor gates. Integrated circuit CMP models focus on oxide and other dielectrics, as well as on the polishing of copper interconnects. MEMS CMP must cover a broader set of standard and non-standard materials, such as silicon carbide [1]. Our study examines the polishing of polysilicon, a structural material used widely in MEMS devices [2]. Another important difference between IC and MEMS CMP relates to wafer bonding, an enabling technology for many types of MEMS devices. Fabrication creates die and wafer level features, but also increases surface roughness that can impede bonding; CMP can be used for surface preparation to decrease the surface topography and roughness, and can enable previously non-bonding wafer pairs to bond [3]. At the same time, the polishing process will also affect the wafer’s structural patterns. CMP may result in global nonplanarity caused by differences in pattern size or density across the die or wafer. We model the CMP process using an analytical model originally proposed by Stine et al. [4]. This model produces analytical solutions for polishing based on effective pattern density across the target die [5]. Central to this model is the idea of planarization length, the distance over which the CMP process creates local planarization, but fails to remove global nonplanarity. The step height density model [6, 7] extends the effective density model by incorporating material r
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