AIDA-C Layout-Aware Circuit Sizing Results
This chapter presents and discusses the results obtained with the proposed analog integrated circuit (IC) sizing approach, where layout effects are included in the optimization loop by considering the circuit’s floorplan and layout induced parasitics. The
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tomatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
Nuno Lourenço Ricardo Martins Nuno Horta •
Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects
123
Nuno Lourenço Instituto de Telecomunicações, Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal
Nuno Horta Instituto de Telecomunicações, Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal
Ricardo Martins Instituto de Telecomunicações, Instituto Superior Técnico Universidade de Lisboa Lisbon Portugal
ISBN 978-3-319-42036-3 DOI 10.1007/978-3-319-42037-0
ISBN 978-3-319-42037-0
(eBook)
Library of Congress Control Number: 2016945775 © Springer International Publishing Switzerland 2017 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. Printed on acid-free paper This Springer imprint is published by Springer Nature The registered company is Springer International Publishing AG Switzerland
To Alina and Íris Nuno Lourenço To my little girls, Nádia, Joana and Daniela Ricardo Martins To Carla, João and Tiago Nuno Horta
Preface
Over the past few decades, very large scale integration technologies have been widely improved, allowing the proliferation of consumer electronics and enabling the steady growth of the integrated circuit (IC) market to an estimated value of over $350 billion in 2016. The steady increase in performance of ICs in the recent past has been mostly supported by an exponential growth in the density of transistors while inversely reducing the transistors’ cost, as described by Moore’s law. Even though it is still valid today, its end, as such an exponential law “can’t continue forever” was already preconized by Moore itself, and is pushing for new technologic advancements outside complementary metal-oxide-semiconductor (CMOS) IC design. In the meanwhile, telecommunications, medical, and multimedia applications ext
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