Fabrication process, experimental results, and application for an elemental level vertically intergrated circuit (ELVIC)
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(Received 20 February 1986; accepted 27 May 1986) A new double-layered stacked LSI fabrication process has been developed for the purpose of realizing short fabrication turn-around time, high fabrication yield, and high integration density. This process, which is named “Elemental Level Vertical Integrated Circuit (ELVIC)” technology, puts two conventionally made LSI chips face to face and bonds them by thermal compression. The process includes, in addition to the conventional LSI fabrication process, vertical interconnection (VI ) formation in the upper and lower LSI layers, planarization of both upper and lower layer surfaces, and inter-level connections using pressure and heat. In the experimental version, about 52 OOO 10x 10,um2Au-on-Ti VIs were connected on a 5 X 5 mm2 chip. Each pair of mated VIs was measured and had a tensile strength of 4 mg force. A two-layer, 3 I-stage inter-CMOShulk ring oscillator consisting of p-channel MOSFETs on the upper layer and n-channel MOSFETs on the lower layer has been built. Propagation delay time per stage is 1.86 ns at the supply voltage of 5 V. ELVIC technology can produce a variety of benefits such as high production yield, doubling integration density, latchup-free CMOS LSIs, radiation-damage-free LSIs, multifunction, and complete mixing of bipolar, CMOS, and GaAs technologies.
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1. INTRODUCTION Multilayer LSIs are expected to increase integration density much higher compared to conventional LSIs, so that the super parallel signal processing function is expected to be realized resulting in performing extremely high-speed signal processing. Furthermore, since many sophisticated and huge circuitries can be fabricated on a single multilayer chip, a large variety of digital signal processing systems can easily be constructed. One of the most promising techniques to realize such multilayer LSIs is to use semiconductor-on-insulator (SOI) technology for which active elements such as transistors are made using recrystallized semiconductor films. However, there presently exist many disadvantages in this technology such as longer turnaround time (TAT), low productivity, low fabrication yield, poor device reliability, etc. These disadvantages must be overcome. Furthermore, in order to realize such multilayer LSIs, many breakthroughs in fabrication technology must be developed. They are low-temperature recrystallization, low-resistivity refractory metal and/or metal-silicide interconnection fabrication, surface planarization, and others. These technologies are either under development or have not been yet developed, so that integration densities of the devices previously reported have, of necessity, remained small and the number of active layers of the devices has been limited to only two to three. 1,2 The purpose of this work is to develop a new fabrication technology for a two-layer stacked LSI structure 552
J. Mater. Res. 1 (4), Jul/Aug 1986
http://journals.cambridge.org
without using any of the new technologies stated above with the goal of further refining the above-stated
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