Al-mediated Solid-Phase Epitaxy of Silicon-On-Insulator
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1245-A20-03
Al-mediated Solid-Phase Epitaxy of Silicon-On-Insulator Agata Šakić, Yann Civale, Lis K. Nanver, Cleber Biasotto, and Vladimir Jovanović Laboratory of Electronic Components, Technology and Materials, Delft Institute of Microsystems and Nanoelectronics – DIMES, Delft University of Technology, Feldmannweg 17, 2628CT Delft, The Netherlands. Tel: +31 (0)15 27 82185, Fax: +31 (0)15 26 22 163, E-mail: [email protected] ABSTRACT Silicon-on-insulator (SOI) regions have been grown on lithographically predetermined positions by Al-mediated Solid-Phase Epitaxy (SPE) of amorphous silicon (α-Si). A controllable Si lateral overgrowth is induced from windows formed in silicon dioxide (SiO2) to the crystalline Si substrate. The resulting hundred-of-nanometer large areas of high-quality monocrystalline SOI are formed at the temperatures that can be as low as 400 °C. The as-obtained SOI regions were found to take on the same crystal orientation as the (100)-Si substrate and have the ability to merge seamlessly over the oxide. INTRODUCTION Recently an Al/α-Si SPE process was demonstrated, where an Al-mediation of the α-Si on a monocrystalline Si substrate was shown to provide high-quality Al-doped crystalline Si islands on predetermined positions. With this process, near-ideal, ultra-shallow, ultra-abrupt p+n-junctions down to sub-100-nm dimensions were formed in contact windows to an n-substrate [1, 2]. In the present paper this Al-mediated SPE process is used to obtain silicon-on-insulator (SOI) regions around the contact windows. Such SOI processes are particularly interesting for ultra-high-scale integration systems and three-dimensional integrated circuits (3D-IC) [3]. Moreover, large investments are at present being made in bonded SOI wafers for the purpose of serving fully-depleted CMOS SOI production. Compared to bulk-Si devices, the SOI version is usually more latch-up resistant, has reduced parasitic capacitances, facilitates the fabrication of shallow junctions and has better radiation hardness. Among many studied SOI technologies, Lateral Solid-Phase Epitaxy (L-SPE) of α-Si silicon films deposited on SiO2 and Si surfaces has been promising mainly due to its low process temperatures. It has also been found that the annealing under ultra-high pressure up to 2 GPa increases further the growth and nucleation rate. However, reported cases suffer from unexpected oxide films formed on the surface of the grown silicon layers [4], or are limited to long annealing times up to 120h at about 600 °C [5]. In this paper, we characterize and evaluate for the first time the Al-mediated L-SPE for anneal cycles as short as 30 min at 400 °C, and for a range of different geometries and SiO2/Al/α-Si stack thicknesses. EXPERIMENTAL PROCEDURES To investigate the possibility of controlling the epitaxial Si lateral overgrowth on SiO2, the samples were subjected to variety of process modifications. A schematic of the basis process flow is shown in Fig. 1. Contact windows were etched through 30 nm, 70 nm, and 100 nm of oxide grown on a
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