All-CSS processing of CdS/CdTe thin-film solar cells with thin CdS layers
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1012-Y03-23
All-CSS processing of CdS/CdTe thin-film solar cells with thin CdS layers Alan R. Davies1, J. R. Sites1, R. A. Enzenroth2, W. S. Sampath2, and K. L. Barth2 1 Physics, Colorado State University, 1875 Campus Delivery, Fort Collins, CO, 80523 2 Mechanical Engineering, Colorado State University, Fort Collins, CO, 80523
ABSTRACT Cadmium sulfide/cadmium telluride (CdS/CdTe) thin-film solar cells were fabricated by an in-line, close-space-sublimation (CSS) process. Source temperature control was used to reduce the deposited CdS thickness. Quantum efficiency (QE) showed CdS thicknesses that varied over a range from 250 to 10 nm. Current-Voltage (J-V) measurements showed increased Jsc as CdS was thinned. Thin CdS resulted in reduced voltage (800 mV to 350 mV) and fill factor, which offset gains in current, and caused efficiencies to drop from 12.6% for thick CdS layers to 4.5% for devices with the thinnest CdS. These performance trends are consistent with calculations assuming parallel junctions of CdS/CdTe and SnO2/CdTe. Localized weak-junction formation was characterized by high-resolution laser-beam-induced current (LBIC) mapping. Greater incidence of spatial non-uniformities in photocurrent response accompanied thinning of the CdS layer, with 638-nm spectral response varying spatially by 4.5% for thin CdS devices compared to variations less than 1% for devices with thicker CdS. Non-uniformities of cells with thin CdS are highly sensitive to voltage bias and are likely indicative of parallel p-n and Schottky-type junctions. INTRODUCTION The CdTe thin-film solar electric market has enjoyed substantial recent growth, and new entries to the market are honing the technology for high efficiency CdS/CdTe modules while attempting to further reduce production cost. Simplification of the fabrication process is an attractive route to more economical PV modules. Maintaining a consistent deposition method for all layers allows for manufacturing in an in-line configuration and for compactness of deposition equipment. Specifically, an all-vapor process for CdS and CdTe layers has advantages over combination processes (CBD CdS and vapor CdTe for example), due to the elimination of waste by-products inherent in the wet process, and the facilitation of a single vacuum chamber, with neighboring deposition stations. However, wet processing of the CdS layer in particular has to date yielded superior layer uniformity [1], or allowed more reliable thinning of the window and greater current generation. Non-uniform CdS layers, and particularly those with large grains are more likely to have a high density of pin-holes, allowing the formation of so-called ëweakí junctions, which are detrimental to cell and module performance.
The diode saturation current Jo is a controlling parameter determining device Voc and hence performance [2]. The problem of parallel junctions of CdS/CdTe and SnO2/CdTe can be understood in terms of spatial variation of Jo and the non-uniform Voc model of Kanevce [3]. Typical measured values for Jo for a CdS/
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